Spansion recently introduced a NOR flash that the company boasts is the: “World’s fastest NOR flash memory”. Named HyperFlash, the chip taps into high-speed SPI interface, doubling its width and adding a differential clock to run at an I/O rates as high as 333MB/s.
In this post’s graphic (click to enlarge) Spansion compares the HyperFlash chip’s sustained read rate (right-hand column) to that of (from left to right) asynchronous parallel NOR, single-bit SPI, industry-standard DDR Quad SPI, and Spansion’s faster rendition of DDR Quad SPI, which Spansion tells us, until now, has been the fastest flash on the market. The company points out that HyperFlash is five times the speed of industry-standard Continue reading “Spansion’s Super-Fast HyperFlash NOR”
At the Flash Memory Summit in August I had the honor of awarding Fujio Masuoka, the inventor of both NAND and NOR flash, the Flash Memory Summit Lifetime Achievement Award. This award is given to the giants of the flash memory industry to acknowledge their contributions.
Dr. Masuoka first described NOR flash at the 1984 International Electron Device Meeting (IEDM) in San Francisco, and NAND flash at the same venue in 1987. His paper “A new flash EEPROM cell using triple polysilicon technology” introduced a technology that is now used everywhere.
The award has also been given to Intel’s Flash team who brought the first commercial products to the market, and SanDisk co-founder Eli Harari, for devising a way to manufacture a floating gate.
David Schwaderer made a video of the presentation and posted it HERE. Have a watch!
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have determined to take this route. Why is that?
In Spansion’s case, a charge trap was a means of doubling the bit capacity of its products. It was an inexpensive alternative to standard MLC flash. To date this strategy has worked very well.
As mentioned in that earlier post, 3D NAND uses a charge trap because it’s extremely difficult to create features, like a floating gate, sideways – lithography works from the top down. A charge trap, when used to replace a floating gate, doesn’t need to be patterned, since the Continue reading “3D NAND: Benefits of Charge Traps over Floating Gates”
From time to time I am asked: “Why is NAND flash called NAND?” or “Why do we say RAM?” and similar questions. A lot of this has to do with history, and a lot of terminology which is now obsolete. To understand these strange names, you have to understand the history of memories. The Computer History Museum (CHM) in Silicon Valley is a great help in this vein.
Since the Memory Guy has been in Silicon Valley since 1977, a lot of this information is stored in my head. Let me try to share it with you in a way that I hope will make more sense, and will help outsiders to understand these odd names.
Here’s the history of memory nomenclature, as I understand it: Continue reading “Why Do Memories Have Those Odd Names?”
Just in case anyone thought that NOR flash was not going to get any denser, Spansion announced a single-chip 8Gb parallel NOR today. This product, built using Spansion’s MirrorBit technology on a 45nm line is not only the densest monolithic NOR chip on the market, it’s also the NOR flash with the finest process technology.
Spansion’s GL-T product is aimed at applications that need high densities at read speeds faster than those that NAND flash can deliver. Spansion tells The Memory Guy that read performance is 95MB/s and program performance is 1.8 MB/s.
Sampling will commence in December, with production in the first quarter of 2013.
Today I saw an announcement from another market research firm about a new report with flash memory market shares for 2011. I found it remarkable that the way these chips are counted varies enough that the company decided to openly discuss this issue right in the press release for the report!
Memory market statistics are compiled by numerous firms: The World Semiconductor Trade Statistics (WSTS) sold in the US and Europe by the Semiconductor Industry Association (SIA), Gartner Dataquest, IHS iSuppli, Web Feet, Semico, Forward Insights, and even DRAMexchange. Lots of entities use conflicting definitions of what is and what is not a chip. This causes each company’s numbers to differ from the others’.
In the case of WSTS, a chip that is packaged with another chip into a board becomes Continue reading “Figuring Out Who Shipped What”
SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.
These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”
The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.
The companies have also agreed to cross-license their patent portfolios.
You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”
Nostalgia buffs who lived through computing in the 1970s will enjoy some magnificent photos shared in comments to a Microcontroller Central blog post. The photos, shared by Ryszard Milewicz, give a close-up view of a ferrite core memory plane. The photo from this blog is a part of one of Mr. Milewicz’ photos.
For those who were not exposed to core, this technology was based upon an approach in which every individual bit of a computer’s memory was a tiny donut made of compressed iron powder (“Ferrite”) that had to be hand strung with copper wire into a plane of bits.
A co-worker of The Memory Guy once had a high-speed memory array that he used as Continue reading “Remembering Core Memory”
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading “IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?”
The current battle between Cypress Semiconductor and GSI Technology caught The Memory Guy’s eye recently. Many readers may have missed this battle that commenced when Cypress filed a Federal Trade Commission (FTC) lawsuit in the US in which the company asked for GSI SRAMs to be barred from importation into the US because of a patent dispute.
GSI has issued a countersuit with a complaint of anticompetitive practices.
What garnered my interest is how similar the tactics in this lawsuit are to those used for some of the Rambus lawsuits that evolved over the years: Continue reading “Cypress vs. GSI Battle Following Rambus Lead”