Microchip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies. It’s as fast as an SRAM with the nonvolatility of an EEPROM.
Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”
The Memory Guy has found that some people get confused about the terminology surrounding flash “Layers” and “Levels,” Sometimes confusing the two, and often misunderstanding what each one means. This post is meant to be a low-level primer to address that confusion.
There are actually three places where such terminology is used: The number of chips in a package, the number of conductor/insulator pairs in 3D NAND, and the number of voltage levels stored on any single bit cell within the chip. I will address them in that order.
CHIP STACKING: Since the 1990s Both NAND and NOR flash chip makers have been stacking chips within a single plastic package. Originally this approach was used to reduce the size of thin flip phones like the Motorola Razr by stacking an SRAM chip on top of NOR flash, but soon afterwards NAND chips began to use the same approach to get incredible storage capacities into a single IC package or eMMC, or into a microSD card format. What began as 2-die stacks became 4, then 8, and now 16 high. This post’s photo illustrates an 8-high stack.
Since the height of a standard plastic package for a chip is smaller than a stack of 16 full-thickness dice the wafers had to be Continue reading “NAND Flash’s Layers of Layers of Layers”
Last year I stumbled upon something on the Internet that I thought would be fun to share. It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes. The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.
On the horizontal axis is Access Time, which the storage community calls latency. The vertical axis shows cost per bit. The chart uses a log-log format: both the X and Y axes are in orders of magnitude. This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.
What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented. First, let’s talk about the technologies.
At the very top we have RAM: “TTL, ECL, and fast MOS static types.” TTL and ECL, technologies that are seldom Continue reading “Storage/Memory Hierarchy 40 Years Ago”
My colleague Lane Mason found an interesting history of memories blog post that answers the question: ” What did early computers use for fast read/write storage?”
The post in the Hackaday blog, written by Al Williams, covers drum memories, the Williams Tube and its competitor the Selectron (both briefly discussed in my earlier 3D XPoint post), mercury delay lines, dekatrons, core memory (the original Storage Class Memory), plated wire memory, twistor memory, thin-film memory, and bubble memory.
It also links to interesting videos about these devices.
Think of this as a companion piece to the EE Times memory history slideshow I covered in an earlier post. It’s a fun and educational read!
At the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM. Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.
The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop.
The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.
This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual Continue reading “A 1T SRAM? Sounds Too Good to be True!”
With Micron & Intel’s July 28 introduction of their new 3D XPoint memory both companies touted that his is the first new memory in a long time, and that the list of prior new memory types is short.
How short is that list? Interestingly, Intel and Micron have different lists. The Micron list, shown in this post’s graphic (click to enlarge), cites seven types: “Ram” (showing a vacuum tube), PROM, SRAM, DRAM, EPROM, NOR flash, and NAND flash. Intel’s list adds magnetic bubble memory, making it eight. (Definitions of these names appear in another Memory Guy blog post.)
The Memory Guy finds both lists puzzling in that they left out a number of important technologies.
For example, why did Intel neglect EEPROM, which is still in widespread use? EEPROMs (or E²PROMs) are not only found in nearly every application that has a serial number (ranging from WiFi routers to credit cards), requires calibration (like blood glucose monitoring strips and printer ink cartridges), or provides operating parameters (i.e. the serial presence detect – SPD – in DRAM DIMMs), but they still ship in the billions of units every year. In its time EEPROM was an important breakthrough. Over the years EEPROM has had a much greater impact than has PROM.
And, given that both companies were willing to include tubes, a non-semiconductor technology, why did both Continue reading “How Many Kinds of Memory Are There?”
(Excerpted from an Objective Analysis Alert issued 1 December 2014.)
In a move touted as a merger of equals, Cypress will acquire Spansion in an all-stock transaction slated to close in the second quarter of 2015. The purchase price is estimated at $1.6 billion.
Cypress points out that it is the leading producer of SRAMs, and that Spansion is the leading NOR flash provider.
One striking feature of this transaction is the Continue reading “Cypress to Merge with Spansion”
Some time ago The Memory Guy was asked by Numonyx (later acquired by Micron) to put together an online course for EE Times on memory technologies, explaining how each one works and where it is used.
Although the course was very well received, I never posted a link to it on The Memory Guy blog. This post is intended to correct that error.
The course runs 75 minutes and covers the basics of DRAM, non-volatile RAM, SRAM, NAND flash, NOR flash, mask ROM, and EEPROM. It explains each technology’s advances in size, cost and performance, leading up to the development of Continue reading “Fundamentals of Memory – Free Online Course”
From time to time I am asked: “Why is NAND flash called NAND?” or “Why do we say RAM?” and similar questions. A lot of this has to do with history, and a lot of terminology which is now obsolete. To understand these strange names, you have to understand the history of memories. The Computer History Museum (CHM) in Silicon Valley is a great help in this vein.
Since the Memory Guy has been in Silicon Valley since 1977, a lot of this information is stored in my head. Let me try to share it with you in a way that I hope will make more sense, and will help outsiders to understand these odd names.
Here’s the history of memory nomenclature, as I understand it: Continue reading “Why Do Memories Have Those Odd Names?”
The IEEE Spectrum published an interesting article postulating that Russia’s recently-failed Mars probe may have suffered from bad memory chips. According to the Spectrum article the Russian government’s Official Accident Investigation Results faulted SRAMs:
The report blames the loss of the probe on memory chips that became fatally damaged by cosmic rays.
Both the main computer and the backup computer seem to have failed at the same time, Continue reading “IEEE Spectrum: Did Bad Memory Chips Down Russia’s Mars Probe?”