I was saddened to hear last week of the death this month of Simon Sze, the co-inventor of the floating gate, which was the basis of EPROM, E²PROM, and nearly all flash memory prior to the advent of 3D NAND, which uses a charge trap instead.
Dr. Sze was not only responsible for the floating gate, but he was a pioneer in Continue reading “Remembering Simon Sze”
In this post in The Memory Guy blog, the first of a 2-part series, Ron Neale returns to explore the present state-of-play for chalcogenide-based switching and memory, with a plea for continuation of research. Along the way he invokes a three-point law for determining the probability of success for would be emerging memory entrepreneurs.
Does PCM still have a chance to become an important new memory technology? Intel’s abandonment of their Optane memory project, while sad, after so much effort and expense, does not and should not Continue reading “The Future of Chalcogenide Switching”
The Memory Guy is pleased to announce the availability of a new Objective Analysis Brief, which is our name for a white paper. It’s called The Future of the Data Center.
The paper explores the new horizons of computing, including disaggregation, AI, IoT, etc., and explains the many different memory approaches that are being used or developed to enable these technologies, ranging from computational storage to DDR5 and CXL
Look for it at the top of the list of free documents on our White Papers page at Objective-Analysis.com.
Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future. That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next. This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”
Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices for the past year. In this second post of a two-part series The Memory Guy will present other companies’ similar PIM devices, and will discuss the PIM approach’s outlook for commercial success.
Part 1 of this series explains the concept of Processing in Memory (PIM), details Samsung’s Aquabolt-XL design, and shares some performance data. It can be found HERE.
Samsung’s Not the First PIM Maker
This is not at all the first Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)”
This week five more Objective Analysis Briefs have just become available. This handful covers commonly held myths and the basic underpinnings of semiconductor market cycles. All are drawn from the most interesting and timeless of the Insights that we have published on membership website Smartkarma. Now Objective Analysis is providing them to our friends for a reasonable price.
The Brief is a very Continue reading “More New Objective Analysis Briefs Available”
For the past year, since ISSCC in February 2021, Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices. In this two-part post The Memory Guy will explain the Aquabolt-XL architecture, its performance, other companies’ similar devices, and discuss the PIM approach’s outlook for commercial success.
Processing in memory is not a Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)”
Although Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves. To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.
The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”
During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.
This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip. The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”
In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”