New White Paper: The Future of the Data Center

Fuzzy photo of the first page of the white paperThe Memory Guy is pleased to announce the availability of a new Objective Analysis Brief, which is our name for a white paper.  It’s called The Future of the Data Center.

The paper explores the new horizons of computing, including disaggregation, AI, IoT, etc., and explains the many different memory approaches that are being used or developed to enable these technologies, ranging from computational storage to DDR5 and CXL

Look for it at the top of the list of free documents on our White Papers page at Objective-Analysis.com.

 

How 3D NAND Makes QLC and PLC Feasible

Four groups of dots representing the number of voltage levels in MLC, TLC, QLC, and PLC flash.Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future.  That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next.  This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”

Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)

Sketch of a sledgehammer driving a wedge into a logSamsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices for the past year.  In this second post of a two-part series The Memory Guy will present other companies’ similar PIM devices, and will discuss the PIM approach’s outlook for commercial success.

Part 1 of this series explains the concept of Processing in Memory (PIM), details Samsung’s Aquabolt-XL design, and shares some performance data.  It can be found HERE.


Samsung’s Not the First PIM Maker

This is not at all the first Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)”

More New Objective Analysis Briefs Available

Five briefs on top of each otherThis week five more Objective Analysis Briefs have just become available.  This handful covers commonly held myths and the basic underpinnings of semiconductor market cycles.  All are drawn from the most interesting and timeless of the Insights that we have published on membership website Smartkarma.  Now Objective Analysis is providing them to our friends for a reasonable price.

The Brief is a very Continue reading “More New Objective Analysis Briefs Available”

Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)

Sketch of a sledgehammer driving a wedge into a logFor the past year, since ISSCC in February 2021, Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices.  In this two-part post The Memory Guy will explain the Aquabolt-XL architecture, its performance, other companies’ similar devices, and discuss the PIM approach’s outlook for commercial success.

Processing in memory is not a Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)”

Introducing New Objective Analysis Briefs

Five briefs on top of each otherAlthough Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves.  To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.

The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”

Did Samsung Just Endorse YMTC’s Xtacking?

Closeup of Samsung graphic, showing illustration of wafer-bonded NANDDuring his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me.  He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.

This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip.  The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”

Weebit-Nano’s First Small Steps on the NV Memory Road

Photo of Ron Neale, Renowned Phase-Change Memory ExpertIn this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France.   Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.


Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”

New Report: Emerging Memories Take Off

Fighter Jets Doing Acrobatic Take-OffThe Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.

The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”