IBM Put PCM at the Core of Hyperdimensional Computing (HDC)

Photo of Ron Neale, Renowned Phase-Change Memory ExpertOur PCM maven Ron Neale explored how PCM is being used to benefit Artificial Intelligence (AI) and Machine Learning (ML) applications.  Although AI is a new spin to The Memory Guy blog, there is a striking similarity between memory chips and certain AI applications, most particularly Neural Networks.

In this post Ron delves into a recent piece of IBM research published in Nature Electronics, that uses Hyperdimensional Computing algorithms to Continue reading “IBM Put PCM at the Core of Hyperdimensional Computing (HDC)”

Applied Materials Video Dramatizes 3D NAND Manufacture

Visualization of a column of ions etching a holeIn a little 3-minute video released this  week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.

For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”

SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry

I attended a bit of the SPIE Advanced Lithography conference in San Jose this  week.  This  show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology.  Still, there were certain aspects that I wanted to see.  Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”

NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)

Ron NealeIn this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.

Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application.  These were discussed in the first part of this series.

However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.

The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”

Gordon Moore’s Original 1965 Article

The Memory Guy recently received a question asking where to find Gordon Moore’s famous paper on Moore’s Law.  It seems that Moore’s seminal 1965 article is not very easy to find on the web.

I did a little digging myself and found a copy for ready download.  It’s still good reading.  The Computer History Museum gives access to the original 1965 article.  This page also features a follow-up article written ten years later in 1975, and a 1995 thirty-year review of the  phenomenon.

All are worth reading.

Back in 2010 I was able to attend the International Solid State Circuits Conference (ISSCC) in which Moore presented a keynote speech that looked back from an even more distant perspective.  A little digging found this presentation on The Engineering and Technology History Wiki in the form of a script and downloadable slides.  The presentation is titled “No Exponential is Forever“.  Although I know that Continue reading “Gordon Moore’s Original 1965 Article”

Why DRAM is Threatened by SSDs

Memcon Slide on FlashConventional wisdom holds that SSDs will someday displace all HDDs, but in reality SSDs are proving to be more of a challenge to the DRAM market than to the HDD market.

Right now you are probably reviewing the date of this post to make sure it’s not dated April 1.  I assure you that this is the truth.  To understand it, though, you must look at a computer as a computer architect would, or, in other words, the way that an application program sees the memory/storage hierarchy.

To the application program there is no HDD and memory, there is only memory.  The Virtual Memory system, a part of the operating system, hides the difference between the two by moving code and data into DRAM as it is needed and back onto the HDD when it is no longer important, without telling the application program that it is moving anything around.  I like to tell people that the DRAM makes the HDD look fast, and the HDD makes the DRAM look big.

If you think of the DRAM as something that makes the HDD look fast, then additional DRAM should help to make the Continue reading “Why DRAM is Threatened by SSDs”

Solving 3D NAND’s Staircase Problem

Escher Staircase3D NAND presents an interesting conundrum.  To improve bit costs and continue along the path of Moore’s Law the layer count must increase.  Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever.  The natural way to reduce costs and increase chip density is by adding layers.

But adding layers increases the size of the staircase structure used to access the wordline layers.

With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles.  At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.

An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”

How Samsung Will Improve 3D NAND Costs

Samsung's New Stairstep Etch iOne of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND.  This was one of numerous innovations the company’s  EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.

The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there.  Samsung seems to have a policy that prohibits sharing such presentations.

Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel!  The result is the graphic for this blog post.  The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND.  You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.

Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago.  This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”

3D NAND: “I Have More Layers than You Do!”

Layer CountYesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.

Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”

The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.

The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time.  By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).

WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers.  The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.

One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””

Examining 3D XPoint’s 1,000 Times Endurance Benefit

3D XPoint Endurance GraphicThe Memory Guy, as a regular reader of The SSD Guy’s posts, found an interesting one that compares the endurance of Optane SSDs against that of NAND flash SSDs.  Perhaps this could provide some insight into the Intel & Micron claim that 3D XPoint Memory’s endurance is 1,000 times that of standard NAND flash, shown in the graphic to the left.

The SSD Guy post converts several different measures of SSD endurance against each other: TBW, DWPD, and GB/Day.  Definitions of these terms can be found in that post.

It occurred to me that any of these can be used to roughly gauge the relative endurance of 3D XPoint Memory against that of NAND flash.

Take DWPD for example: Drive Writes per Day.  Not only is this a measure of how many times that an SSD can be over-written every day, but it’s also an indication of the number of times that each memory cell can be overwritten.  If you know this, and if you know how long Continue reading “Examining 3D XPoint’s 1,000 Times Endurance Benefit”