This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not Continue reading “64-Layer 3D NAND Chips Revealed at ISSCC”
A very unusual side effect of the move to 3D NAND will be the impact on the equipment market. 3D NAND takes the pressure off of lithographic steps and focuses more attention on deposition and etch. The reason for going to 3D is that it provides a path to higher density memories without requiring lithographic shrinks.
This sounds like bad news for stepper makers like ASML, Canon, and Nikon while it should be a boon to deposition and etch equipment makers like Applied Materials, Tokyo Electron, and Lam Research.
In its summer 2013 V-NAND announcement, Samsung explained that it would be Continue reading “3D NAND’s Impact on the Equipment Market”
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?”
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”
A prior post in this series (3D NAND: Making a Vertical String) discussed the difficulties of successfully manufacturing a charge trap flash bit. Still, Spansion, and now other flash makers, have determined to take this route. Why is that?
In Spansion’s case, a charge trap was a means of doubling the bit capacity of its products. It was an inexpensive alternative to standard MLC flash. To date this strategy has worked very well.
As mentioned in that earlier post, 3D NAND uses a charge trap because it’s extremely difficult to create features, like a floating gate, sideways – lithography works from the top down. A charge trap, when used to replace a floating gate, doesn’t need to be patterned, since the Continue reading “3D NAND: Benefits of Charge Traps over Floating Gates”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”
SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.
These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”
The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.
The companies have also agreed to cross-license their patent portfolios.
You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”