(The following is an update of a post that originally ran 25 October 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
In the prior post we discussed the need to go vertically into the body of the die, since NAND flash can not Continue reading “What is a 3D NAND?”
(The following is an update of a post that originally ran 18 October 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost Continue reading “Why Do We Need 3D NAND?”
Back in 2013, when Samsung announced its V-NAND, the first production 3D NAND, The Memory Guy blog carried a series of posts to explain the new technology and the reason it was so necessary.
Now that the inventors of this technology have been honored with the FMS Lifetime Achievement Award, I decided that it was time to refresh that series of blog posts. Once a week for the next nine weeks I will be reissuing a post in this series. I hope that these will Continue reading “What is 3D NAND? Why do we need it? How do they make it?”
I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”
Last week Toshiba and SK hynix announced an agreement to jointly develop Nano Imprint Lithography (NIL), building on a memorandum of understanding (MOU) that two companies signed in December last year. Development efforts will begin this April and practical adoption is expected to start in 2017. The collaboration is expected to reduce risk and accelerate commercialization of this technology.
NIL is expected to produce next-generation lithography at high throughput rates more economically than established lithography tools. It is should compete against Extreme Ultraviolet (EUV) lithography, an alternative technology whose use has been delayed by numerous technical challenges. EUV, a euphemism for X-Rays, cannot use transmissive optics like glass lenses, so a completely new reflective imaging technology has had to be developed to support its use. The advantage of EUV is that the light wavelength is only 13nm, which is an order of magnitude smaller than the 193nm light currently used to produce leading-edge chips, allowing it to print significantly smaller features.
Unlike today’s lithography, which uses a purely photographic process, NIL mechanically stamps a pattern into the photoresist in a similar manner to the sealing wax stamp shown in the photo (courtesy of BackToZero, a wax stamp maker). The stamp is produced using Continue reading “What’s This Nano-Imprint Litho that Toshiba and SK hynix are Co-Developing?”
NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”
This year’s Kyoto Prizes included an Advanced Technology Prize for the father of DRAM, IBM’s Dr. Robert Dennard.
The Kyoto Prize, one of the world’s most prestigious accolades, is an international award bestowed once a year by The Inamori Foundation to honor those who have contributed significantly to the scientific, cultural and spiritual betterment of humankind. Some say it is similar to the Nobel Prize, and seven Kyoto Prize laureates have gone on to win the Nobel Prize.
In addition to the kudos of receiving this honor, Denning was also Continue reading “DRAM Inventor Wins Kyoto Prize”
During the Flash Memory Summit last August Facebook’s Jason Taylor, Director of Capacity Engineering and Analysis, asked in his keynote speech for a flash chip with dramatically lower cost per gigabyte, saying that he would readily give up speed and endurance to achieve this lower cost. Taylor called this “Cold Flash” and said he was willing to use something that was “Write Once, Read Many” or WORM for data that was unlikely to change over its lifetime. He said this was Facebook’s “Ask of the Industry.”
That same sentiment was echoed yesterday at Samsung’s Memory Solutions Forum by eBay’s Distinguished Engineer and Technologist Roark Hilomen, who said that he could live with 1/3rd the number of writes that normal flash supports as long as he could get it for 1/4 the price.
Unfortunately this is simply not possible.
Let’s do a little math to understand Continue reading “Why Facebook Can’t Get its Dream Memory Chip”
Just in case anyone thought that NOR flash was not going to get any denser, Spansion announced a single-chip 8Gb parallel NOR today. This product, built using Spansion’s MirrorBit technology on a 45nm line is not only the densest monolithic NOR chip on the market, it’s also the NOR flash with the finest process technology.
Spansion’s GL-T product is aimed at applications that need high densities at read speeds faster than those that NAND flash can deliver. Spansion tells The Memory Guy that read performance is 95MB/s and program performance is 1.8 MB/s.
Sampling will commence in December, with production in the first quarter of 2013.
SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.
These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”
The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.
The companies have also agreed to cross-license their patent portfolios.
You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”
