Vertical Structures – The Memory Guy

Weebit-Nano’s First Small Steps on the NV Memory Road

In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.

Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”

New Report: Emerging Memories Take Off

The Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.

The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”

ZnTe Selectors to Solve NVM Fabrication Problems

Contributor Ron Neale joins us again to review a recently-published article in the journal Nature Scientific Reports. While the main focus of the paper is on using a nitrogen environment to generate stable memory selectors from ZnTe, it also provides some new inputs through which he finds further support of his theories of Forming and device behavior.

A recently-published Nature Scientific Reports article by a research team from Hanyang and Kunsan Universities in The Republic of Korea focuses on Continue reading “ZnTe Selectors to Solve NVM Fabrication Problems”

Why 3D NAND is Stuck at 40nm

I recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction. Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then. Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?

The Memory Guy’s reply was that it’s nearly impossible Continue reading “Why 3D NAND is Stuck at 40nm”

The Invention of Charge Trap Memory – John Szedon

A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.

Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”

Applied Materials Video Dramatizes 3D NAND Manufacture

In a little 3-minute video released this week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.

For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”

SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry

I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”

NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)

In this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.

Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.

However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.

The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”

Solving 3D NAND’s Staircase Problem

3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.

But adding layers increases the size of the staircase structure used to access the wordline layers.

With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.

An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”

How Samsung Will Improve 3D NAND Costs

One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND. This was one of numerous innovations the company’s EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.

The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there. Samsung seems to have a policy that prohibits sharing such presentations.

Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel! The result is the graphic for this blog post. The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND. You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.

Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago. This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”