Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future. That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next. This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”
Category: Vertical Structures
Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)
Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices for the past year. In this second post of a two-part series The Memory Guy will present other companies’ similar PIM devices, and will discuss the PIM approach’s outlook for commercial success.
Part 1 of this series explains the concept of Processing in Memory (PIM), details Samsung’s Aquabolt-XL design, and shares some performance data. It can be found HERE.
Samsung’s Not the First PIM Maker
This is not at all the first Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)”
Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)
For the past year, since ISSCC in February 2021, Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices. In this two-part post The Memory Guy will explain the Aquabolt-XL architecture, its performance, other companies’ similar devices, and discuss the PIM approach’s outlook for commercial success.
Processing in memory is not a Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)”
Did Samsung Just Endorse YMTC’s Xtacking?
During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.
This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip. The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”
Weebit-Nano’s First Small Steps on the NV Memory Road
In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”
New Report: Emerging Memories Take Off
The Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.
The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”
ZnTe Selectors to Solve NVM Fabrication Problems
Contributor Ron Neale joins us again to review a recently-published article in the journal Nature Scientific Reports. While the main focus of the paper is on using a nitrogen environment to generate stable memory selectors from ZnTe, it also provides some new inputs through which he finds further support of his theories of Forming and device behavior.
A recently-published Nature Scientific Reports article by a research team from Hanyang and Kunsan Universities in The Republic of Korea focuses on Continue reading “ZnTe Selectors to Solve NVM Fabrication Problems”
Why 3D NAND is Stuck at 40nm
I recently was asked how much 3D NAND pitches had shrunk since the technology’s 2013 introduction. Samsung made a big to-do about using 40nm back in 2015, but the company and its competitors don’t seem to have given an update since then. Shouldn’t it have gone to smaller processes like 35nm, 25nm, 20nm, etc.?
The Memory Guy’s reply was that it’s nearly impossible Continue reading “Why 3D NAND is Stuck at 40nm”
The Invention of Charge Trap Memory – John Szedon
A significant transition has occurred over the past few years that many people don’t know about: Flash memory has moved almost wholesale from the floating gate bit cells, the process that they had always used before, to charge trap bit cells.
Until 2002 all flash used a floating gate. That year partners AMD & Fujitsu, who later merged Continue reading “The Invention of Charge Trap Memory – John Szedon”
Applied Materials Video Dramatizes 3D NAND Manufacture
In a little 3-minute video released this week for the SEMICON West conference, Applied Materials dramatizes the 3D NAND manufacturing process by using hailstorms for atomic level deposition (ALD) and lightning bolts for etch, all while explaining that the wafer’s surface reaches temperatures hotter than the surface of the sun.
For those who already understand 3D NAND manufacture it’s an interesting Continue reading “Applied Materials Video Dramatizes 3D NAND Manufacture”
