(The following is an update of a post that originally ran 18 October 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
A memory chip of a certain area costs about the same amount to produce, no matter how many bits it holds. Naturally, the more bits you can cram onto this chip, the cheaper the price per bit will be. Low cost is of the utmost Continue reading “Why Do We Need 3D NAND?”
Last week’s FMS conference, originally the Flash Memory Summit, but now the Future of Memory and Storage, saw a strong return of the show’s original excitement and attendance, with numerous presentations on key new technologies, largely AI and CXL, and crowds similar to those before the pandemic. FMS is held in early August every year in Santa Clara, California.
The new name is meant to match the show’s content better than Continue reading “FMS – New Focus and a Heavy AI and CXL presence”
Back in 2013, when Samsung announced its V-NAND, the first production 3D NAND, The Memory Guy blog carried a series of posts to explain the new technology and the reason it was so necessary.
Now that the inventors of this technology have been honored with the FMS Lifetime Achievement Award, I decided that it was time to refresh that series of blog posts. Once a week for the next nine weeks I will be reissuing a post in this series. I hope that these will Continue reading “What is 3D NAND? Why do we need it? How do they make it?”
FMS (formerly the Flash Memory Summit) announced on July 24 that a research team from Kioxia will receive the award for inventing 3D NAND flash at FMS: the Future of Memory and Storage, on August 6 in Santa Clara, California. We hope to see you there as the award is being presented to a member of that team.
The team has five Continue reading “3D NAND Team to Receive FMS Lifetime Achievement Award”
In this post in The Memory Guy blog, the first of a 2-part series, Ron Neale returns to explore the present state-of-play for chalcogenide-based switching and memory, with a plea for continuation of research. Along the way he invokes a three-point law for determining the probability of success for would be emerging memory entrepreneurs.
Does PCM still have a chance to become an important new memory technology? Intel’s abandonment of their Optane memory project, while sad, after so much effort and expense, does not and should not Continue reading “The Future of Chalcogenide Switching”
Something that has really changed over the past few years is the use of an increasing numbers of voltage levels in multi-level cell flash, from SLC, to MLC, to TLC, and then QLC, with the promise of PLC (5 bits per cell) in the foreseeable future. That means each PLC cell must be able to hold 32 voltage levels accurately, and the NAND chip’s control logic must be able to tell one level from the next. This post’s graphic is intended to Continue reading “How 3D NAND Makes QLC and PLC Feasible”
Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices for the past year. In this second post of a two-part series The Memory Guy will present other companies’ similar PIM devices, and will discuss the PIM approach’s outlook for commercial success.
Part 1 of this series explains the concept of Processing in Memory (PIM), details Samsung’s Aquabolt-XL design, and shares some performance data. It can be found HERE.
This is not at all the first Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 2)”
For the past year, since ISSCC in February 2021, Samsung has been strongly promoting its “Aquabolt-XL” Processor-In-Memory (PIM) devices. In this two-part post The Memory Guy will explain the Aquabolt-XL architecture, its performance, other companies’ similar devices, and discuss the PIM approach’s outlook for commercial success.
Processing in memory is not a Continue reading “Samsung’s Aquabolt-XL Processor-In-Memory (Part 1)”
During his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me. He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.
This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip. The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”
In this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France. Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.
Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”
