I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”
In this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.
However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.
The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”
3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.
But adding layers increases the size of the staircase structure used to access the wordline layers.
With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.
An example of a staircase structure can be seen in the Continue reading “Solving 3D NAND’s Staircase Problem”
One of the most intriguing revelations during the Flash Memory Summit two weeks ago was Samsung’s new approach to stairstep etch in 3D NAND. This was one of numerous innovations the company’s EVP of Flash Products & Technologies, Kye Hyun (KH) Kyung, shared during Samsung’s Tuesday Morning keynote presentation.
The Memory Guy would point readers to the pdf of Samsung’s presentation on the Flash Memory Summit website, but it isn’t there, and it’s unlikely to ever be posted there. Samsung seems to have a policy that prohibits sharing such presentations.
Although I was unable to get a copy of the drawing that the keynoter used, I have tried to re-create it using, of all things, Excel! The result is the graphic for this blog post. The only thing I was unable to easily recreate was the different colors representing the layers of the 3D NAND. You’ll need to use your imagination and envision layers of two colors, with all the surfaces exposed on the top being the same color, but at different layers of a 64-layer structure.
Today’s common approach to 3D NAND’s stairstep is to etch a simple step pattern in one dimension, which I illustrated in an early 3D NAND blog post four years ago. This is a challenging Continue reading “How Samsung Will Improve 3D NAND Costs”
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””
The Memory Guy, as a regular reader of The SSD Guy’s posts, found an interesting one that compares the endurance of Optane SSDs against that of NAND flash SSDs. Perhaps this could provide some insight into the Intel & Micron claim that 3D XPoint Memory’s endurance is 1,000 times that of standard NAND flash, shown in the graphic to the left.
The SSD Guy post converts several different measures of SSD endurance against each other: TBW, DWPD, and GB/Day. Definitions of these terms can be found in that post.
It occurred to me that any of these can be used to roughly gauge the relative endurance of 3D XPoint Memory against that of NAND flash.
Take DWPD for example: Drive Writes per Day. Not only is this a measure of how many times that an SSD can be over-written every day, but it’s also an indication of the number of times that each memory cell can be overwritten. If you know this, and if you know how long Continue reading “Examining 3D XPoint’s 1,000 Times Endurance Benefit”
This week both the Toshiba-Western Digital team and Samsung disclosed details of their 64-layer 3D NAND designs at the IEEE’s International Solid-State Circuits Conference (ISSCC). The Memory Guy thought that it would be interesting to compare these two companies’ 64-layer chips against each other and against the one that Micron presented at last year’s ISSCC.
Allow me to point out that it’s no easy feat to get to 64 layers. Not only must the process build all 64 layers (or actually pairs of layers plus some additional ones for control) across the entire 300mm wafer with high uniformity and no defects, but then holes must be etched through varying materials from the top to the bottom with absolutely parallel sides at aspect ratios of about 60:1, that is, the hole is 60 times as deep as it is wide. After this the fab must deposit uniform layers of material onto the sides of these skinny holes without any variation in thickness.
None of these processes have ever been used to build any other semiconductor — it’s all brand new. This is what makes 3D NAND so challenging, and it’s why the technology is already 3 years behind its original schedule.
It’s not easy to tell from the conference papers whether or not Continue reading “64-Layer 3D NAND Chips Revealed at ISSCC”
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”
According to Korean news source Chosenilbo the outage was caused by Continue reading “Samsung Power Glitch – Is It Important?”
Beleaguered Toshiba finally unveiled its restructuring plan on Friday. The plan aims to return the company to profitability and growth through management accountability.
A lot of the presentation focused on the memory business, a shining star of the Toshiba conglomerate, which has so far included appliances, nuclear power plants, and medical electronics.
Toshiba has big plans for its Semiconductor & Storage Products Company, calling it “A pillar of income with Memories as a core business”. The company plans to enhance its NAND flash cost competitiveness by accelerating development of BiCS (Toshiba’s 3D NAND technology) and by expanding its SSD business. There are three parts to this effort:
- Grow 3D NAND production capacity
- Speed up 3D NAND development
- Increase SSD development resources
This post’s graphic is an Continue reading “Toshiba Restructuring: New 3D Fab Coming”
At the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM. Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.
The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop. Click on the post’s graphic above to see the whole diagram of the cell.
The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.
This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual Continue reading “A 1T SRAM? Sounds Too Good to be True!”