Our PCM maven Ron Neale explored how PCM is being used to benefit Artificial Intelligence (AI) and Machine Learning (ML) applications. Although AI is a new spin to The Memory Guy blog, there is a striking similarity between memory chips and certain AI applications, most particularly Neural Networks.
In this post Ron delves into a recent piece of IBM research published in Nature Electronics, that uses Hyperdimensional Computing algorithms to Continue reading “IBM Put PCM at the Core of Hyperdimensional Computing (HDC)”
During Intel’s latest earnings announcement the company provided information to indicate that 3D XPoint, which Intel sells under the name “Optane”, may have finally reached break-even: It may no longer be selling at a loss.
How would The Memory Guy know? Well, in fact, I don’t, but I can make an informed guess.
The chart below shows Continue reading “Did 3D XPoint Costs Reach Break-Even?”
Perhaps the oldest nonvolatile semiconductor memory type is the ferroelectric memory, which recently celebrated its 68th birthday. FRAM predates flash memory, EEPROM, and even UV-erasable EPROM. It’s even older than mask ROM, which wasn’t invented until 1967!
As a matter of introduction to the technology, FRAM, or ferroelectric memory, is a read/write nonvolatile memory technology that performs significantly better than Continue reading “FRAM Turns 68”
The Memory Guy is pleased to announce the release of a new report co-authored by Objective Analysis and Coughlin Associates named: Emerging Memories Find Their Direction. In this report we show that emerging memories, MRAM, ReRAM, 3D XPoint, and other technologies are well on their way to reach $36 billion of combined revenues by 2030.
The report provides invaluable guidance to Continue reading “Emerging Memory Market to Hit $36 Billion by 2030”
Contributor Ron Neale joins us again to review a paper delivered at last December’s IEDM conference by John Moores & Cambridge Universities, IMEC, and the University of Wuhan. While the main focus of the paper is on PCM endurance improvements, it also provides some new inputs, which, with some suggested additions of Neale’s own, might now provide a unified explanation of threshold switching in the chalcogenides. Neale includes discussions of these new ideas with one of the paper’s authors.
One of the most interesting papers at the recent IEDM was presented by a team at: John Moores University Liverpool, and Cambridge University, UK, IMEC, Belgium and the University of Wuhan, China. As its title makes clear, this research has an important target of Continue reading “NVM Selectors: A Unified Explanation of Threshold Switching”
I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”
In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”
On January 22 Processor-In-Memory (PIM) maker UPMEM announced what the company claims are: “The first silicon-based PIM benchmarks.” These benchmarks indicate that a Xeon server that has been equipped with UPMEM’s PIM DIMM can perform eleven times as many five-word string searches through 128GB of DRAM in a given amount of time as the Xeon processor can perform on its own. The company tells us that this provides significant energy savings: the server consumes only one sixth the energy of a standard system. By using algorithms that have been optimized for parallel processing UPMEM claims to be able to process these searches up to 35 times as quickly as a conventional system.
Furthermore, the same system with an UPMEM PIM is said to Continue reading “UPMEM Releases Processor-In-Memory Benchmark Results”
The Memory Guy recently encountered some stories in the press about “UltraRAM” which is the name for a new type of NVRAM developed by researchers at Lancaster University in the UK. These researchers published one paper last June in Nature: Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cells, and another just this month in the IEEE’s Transactions on Electron Devices: Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory.
According to the papers, the new Continue reading “University of Lancaster Invents Yet Another Memory”
Ron Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.
At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”. It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”