Introducing New Objective Analysis Briefs

Five briefs on top of each otherAlthough Objective Analysis has published its “Brief” format white papers for some time, this line has never received the focus that it deserves.  To remedy that, we are taking the most interesting and timeless of the Insights that we have published on membership website Smartkarma and providing them to our friends for a reasonable price.

The Brief is a very short report format used to make a succinct Continue reading “Introducing New Objective Analysis Briefs”

Did Samsung Just Endorse YMTC’s Xtacking?

Closeup of Samsung graphic, showing illustration of wafer-bonded NANDDuring his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me.  He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.

This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip.  The brief way to describe it is to say that Continue reading “Did Samsung Just Endorse YMTC’s Xtacking?”

Free Interactive Webinar: Your New Memory Strategy for SEMICON West

Tom Coughlin and Jim Handy at a podium for the Strage Developer Conference 2017Objective Analysis and Coughlin Associates are hosting a free webinar on November 30 to help SEMICON West attendees get the most out of their show visit.

How can you really benefit from your your show attendance?  What kinds of questions will you be asking to make sure that your emerging memories strategy is on point?  What companies Continue reading “Free Interactive Webinar: Your New Memory Strategy for SEMICON West”

What Exactly IS “Storage Class Memory”?

Single-quadrant chart with Bandwidth runing horizontally and cost vertically. Shows where HDD, DRAM, and NAND flash fit, and has an undefined Storage Class Memory block in the center.If you ask any two people in the computing industry to define the term “Storage Class Memory” you’re likely to get three or more answers.  That’s because the term isn’t well defined anywhere.

Some people use it for emerging memory technologies like MRAM, ReRAM, FRAM, and PCM/XPoint.  Others include NAND flash, even in the form of Continue reading “What Exactly IS “Storage Class Memory”?”

Video: The Inner Workings of SiO ReRAM

A cartoon of the atoms in a memory cell for an oxygen vacancy resistive RAMThis post shares a new and entertaining animation by Charlotte Streeter that offers one interpretation of the inner workings of one type of SiO-based nonvolatile memory like those described in Ron Neale’s most recent post on The Memory Guy.

The video links the observed electrical characteristics to the structural Continue reading “Video: The Inner Workings of SiO ReRAM”

Weebit-Nano’s First Small Steps on the NV Memory Road

Photo of Ron Neale, Renowned Phase-Change Memory ExpertIn this post contributor Ron Neale analyzes Weebit Nano’s recently-announced memory array, based on SiO and an Ovonic Threshold Switch selector developed by CEA-Leti in France.   Ron employs his extensive background in Ovonic devices to try and sleuth out the characteristics of both the memory element and the selector, and to understand some of the inner workings of the cell.


Weebit-Nano (Hod Hasharon, Israel), have recently reported some first steps on the path they have outlined to meet their bold claim of Continue reading “Weebit-Nano’s First Small Steps on the NV Memory Road”

New Report: Emerging Memories Take Off

Fighter Jets Doing Acrobatic Take-OffThe Memory Guy is pleased to announced the release of a new report by Objective Analysis and Coughlin Associates: Emerging Memories Take Off.

The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”

Symetrix: The Next Big Step for FeFETs

Photo of Ron Neale, Renowned Phase-Change Memory ExpertRon Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology.  In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.


Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant Continue reading “Symetrix: The Next Big Step for FeFETs”

Putting the Brakes on Added Memory Layers

Close-up of a part of the blog post's main graphicFor some time two sides of the computing community have been at odds.  One side aims to add layers to the memory/storage hierarchy while other side is trying to halt this growth.

This has been embodied by recent attempts to stop using objective nomenclature for cache layers (L1, L2, L3) and moving to more subjective names that aim to limit any attempt to add another new layer.

This is a matter close to my heart, since Continue reading “Putting the Brakes on Added Memory Layers”

Micron Bows Out of 3D XPoint Business

Photo of Micron's Lehi, Utah, wafer fabrication plantIn an investor conference call today Micron Technology announced that it would discontinue further development of the 3D XPoint memory that the company had developed in partnership with Intel, phasing out production and selling off the Lehi, Utah fab (pictured) that makes 3D XPoint.

Micron said that it has determined that the market for the product is too small to Continue reading “Micron Bows Out of 3D XPoint Business”