Tomorrow’s Memory Technologies

ZnTe Selectors to Solve NVM Fabrication Problems

Contributor Ron Neale joins us again to review a recently-published article in the journal Nature Scientific Reports. While the main focus of the paper is on using a nitrogen environment to generate stable memory selectors from ZnTe, it also provides some new inputs through which he finds further support of his theories of Forming and device behavior.

A recently-published Nature Scientific Reports article by a research team from Hanyang and Kunsan Universities in The Republic of Korea focuses on Continue reading “ZnTe Selectors to Solve NVM Fabrication Problems”

Microchip’s Answer to Emerging Memories

Microchip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies. It’s as fast as an SRAM with the nonvolatility of an EEPROM.

Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”

CeRAM Moves Front and Center on the NV Memory Stage

In this post contributor Ron Neale shares a close look at the new memory announced today by Arm spin-off Cerfe Labs. He provides insight into the operation and composition of this technology which originated at Symetrix, a company that has previously developed FRAM technologies licensed to major semiconductor and capacitor manufacturers.

While many companies seek to offer a nonvolatile (NV) alternative to Flash, with varying degrees of success, something new called a correlated electron memory (CeRAM) has entered Continue reading “CeRAM Moves Front and Center on the NV Memory Stage”

IBM Put PCM at the Core of Hyperdimensional Computing (HDC)

Our PCM maven Ron Neale explored how PCM is being used to benefit Artificial Intelligence (AI) and Machine Learning (ML) applications. Although AI is a new spin to The Memory Guy blog, there is a striking similarity between memory chips and certain AI applications, most particularly Neural Networks.

In this post Ron delves into a recent piece of IBM research published in Nature Electronics, that uses Hyperdimensional Computing algorithms to Continue reading “IBM Put PCM at the Core of Hyperdimensional Computing (HDC)”

Did 3D XPoint Costs Reach Break-Even?

During Intel’s latest earnings announcement the company provided information to indicate that 3D XPoint, which Intel sells under the name “Optane”, may have finally reached break-even: It may no longer be selling at a loss.

How would The Memory Guy know? Well, in fact, I don’t, but I can make an informed guess.

The chart below shows Continue reading “Did 3D XPoint Costs Reach Break-Even?”

FRAM Turns 68

Perhaps the oldest nonvolatile semiconductor memory type is the ferroelectric memory, which recently celebrated its 68^th birthday. FRAM predates flash memory, EEPROM, and even UV-erasable EPROM. It’s even older than mask ROM, which wasn’t invented until 1967!

As a matter of introduction to the technology, FRAM, or ferroelectric memory, is a read/write nonvolatile memory technology that performs significantly better than Continue reading “FRAM Turns 68”

Emerging Memory Market to Hit $36 Billion by 2030

The Memory Guy is pleased to announce the release of a new report co-authored by Objective Analysis and Coughlin Associates named: Emerging Memories Find Their Direction. In this report we show that emerging memories, MRAM, ReRAM, 3D XPoint, and other technologies are well on their way to reach $36 billion of combined revenues by 2030.

The report provides invaluable guidance to Continue reading “Emerging Memory Market to Hit $36 Billion by 2030”

NVM Selectors: A Unified Explanation of Threshold Switching

Contributor Ron Neale joins us again to review a paper delivered at last December’s IEDM conference by John Moores & Cambridge Universities, IMEC, and the University of Wuhan. While the main focus of the paper is on PCM endurance improvements, it also provides some new inputs, which, with some suggested additions of Neale’s own, might now provide a unified explanation of threshold switching in the chalcogenides. Neale includes discussions of these new ideas with one of the paper’s authors.

One of the most interesting papers at the recent IEDM was presented by a team at: John Moores University Liverpool, and Cambridge University, UK, IMEC, Belgium and the University of Wuhan, China. As its title makes clear, this research has an important target of Continue reading “NVM Selectors: A Unified Explanation of Threshold Switching”

SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry

I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”

Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit

In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.

One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”