FRAM Turns 68

Photo of a memory chip next to a paper matchPerhaps the oldest nonvolatile semiconductor memory type is the ferroelectric memory, which recently celebrated its 68th birthday.  FRAM predates flash memory, EEPROM, and even UV-erasable EPROM.  It’s even older than mask ROM, which wasn’t invented until 1967!

As a matter of introduction to the technology, FRAM, or ferroelectric memory, is a read/write nonvolatile memory technology that performs significantly better than Continue reading “FRAM Turns 68”

Emerging Memory Market to Hit $36 Billion by 2030

A compass dial overlaid on tp of a silicon wafer full of memory chipsThe Memory Guy is pleased to announce the release of a new report co-authored by Objective Analysis and Coughlin Associates named: Emerging Memories Find Their Direction.  In this report we show that emerging memories, MRAM, ReRAM, 3D XPoint, and other technologies are well on their way to reach $36 billion of combined revenues by 2030.

The report provides invaluable guidance to Continue reading “Emerging Memory Market to Hit $36 Billion by 2030”

NVM Selectors: A Unified Explanation of Threshold Switching

Photo of Ron Neale, Renowned Phase-Change Memory ExpertContributor Ron Neale joins us again to review a paper delivered at last December’s IEDM conference by John Moores & Cambridge Universities, IMEC, and the University of Wuhan.  While the main focus of the paper is on PCM endurance improvements, it also provides some new inputs, which, with some suggested additions of Neale’s own, might now provide a unified explanation of threshold switching in the chalcogenides.  Neale includes discussions of these new ideas with one of the paper’s authors.


One of the most interesting papers at the recent IEDM was presented by a team at: John Moores University Liverpool, and Cambridge University, UK, IMEC, Belgium and the University of Wuhan, China.  As its title makes clear, this research has an important target of Continue reading “NVM Selectors: A Unified Explanation of Threshold Switching”

SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry

I attended a bit of the SPIE Advanced Lithography conference in San Jose this  week.  This  show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology.  Still, there were certain aspects that I wanted to see.  Surprisingly, none of the presentations that I attended related directly to lithography: Two were about Continue reading “SPIE Advanced Litho Conference: Artificial Intelligence and a Lot of Chemistry”

Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit

Photo of Ron Neale, Renowned Phase-Change Memory ExpertIn this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays.  Another interesting aspect of this same paper was the subject of an earlier post.


One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration.  I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”

UPMEM Releases Processor-In-Memory Benchmark Results

Chip layout of Micron's Automata ProcessorOn January 22 Processor-In-Memory (PIM) maker UPMEM announced what the company claims are: “The first silicon-based PIM benchmarks.”  These benchmarks indicate that a Xeon server that has been equipped with UPMEM’s PIM DIMM can perform eleven times as many five-word string searches through 128GB of DRAM in a given amount of time as the Xeon processor can perform on its own.  The company tells us that this provides significant energy savings: the server consumes only one sixth the energy of a standard system.  By using algorithms that have been optimized for parallel processing UPMEM claims to be able to process these searches up to 35 times as quickly as a conventional system.

Furthermore, the same system with an UPMEM PIM is said to Continue reading “UPMEM Releases Processor-In-Memory Benchmark Results”

University of Lancaster Invents Yet Another Memory

The Memory Guy recently encountered some stories in the press about “UltraRAM” which is the name for a new type of NVRAM developed by researchers at Lancaster University in the UK.  These researchers published one paper last June in Nature:  Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cells, and another just this month in the IEEE’s Transactions on Electron Devices: Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory.

According to the papers, the new Continue reading “University of Lancaster Invents Yet Another Memory”

Observations on the “Universal Law” for NV Memory Cells

Photo of Ron Neale, Renowned Phase-Change Memory ExpertRon Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.


At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”.  It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”

NV Memory Selectors: Forming the Known Unknowns (Part 5)

Phto of Ron Neale, Renowned Phase-Change Memory ExpertIn this final part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing on the nature of the mystery of Forming and a number of the many unanswered questions.


Any search for Forming-Free structures might find some help in the article by Antonin Verdy of Leti titled: Optimized Reading Window for Crossbar Arrays Thanks to Ge-Se-Sb-N-based OTS Selectors.  This article also Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 5)”

NV Memory Selectors: Forming the Known Unknowns (Part 4)

Ron NealeIn this fourth part of a five-part series, contributor Ron Neale continues his analysis of selector technologies, focusing on the nature of the mystery of Forming and a number of the many unanswered questions.


From the discussion and investigations outlined in the earlier parts of this series, there would appear to be a number of options to explain selector Forming, where on the first switching event the threshold switching voltage Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 4)”