The report is the 2021 update of our popular 2020 emerging memories report, and includes detailed technology profiles of MRAM, ReRAM, FRAM, PCM/XPoint and other technologies, profiles of Continue reading “New Report: Emerging Memories Take Off”
Microchip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies. It’s as fast as an SRAM with the nonvolatility of an EEPROM.
Readers may recall that Tom Coughlin and I recently updated Continue reading “Microchip’s Answer to Emerging Memories”
The Memory Guy is pleased to announce the release of a new report co-authored by Objective Analysis and Coughlin Associates named: Emerging Memories Find Their Direction. In this report we show that emerging memories, MRAM, ReRAM, 3D XPoint, and other technologies are well on their way to reach $36 billion of combined revenues by 2030.
The report provides invaluable guidance to Continue reading “Emerging Memory Market to Hit $36 Billion by 2030”
Almost one year ago Tom Coughlin and The Memory Guy presented the findings of our first emerging memories report at the Storage Networking Industry Association’s (SNIA) Storage Developers Conference (SDC). The podcast of this presentation has just been made available on the SNIA website.
In the podcast, titled “The Long and Winding Road to Persistent Memories,” Tom and I reviewed leading emerging memory technologies as we had surveyed them for our report.
This is a highly visual presentation, so I would recommend following along with the slides, which can also be downloaded from the SNIA SDC website at HERE. That same page combines the slides and the podcast into a video, so if you’re able to, it might be a good idea to watch the video. If you’re driving as your listening to it, though, then please use the podcast instead!
In the time since that podcast was recorded Tom and I have updated the report to a 2019 edition, which can be Continue reading “Podcast: Storage Developer Conference 2018 – Emerging Memories”
In this third part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
From Part 2 of this series it is very clear that only a detailed and accurate description of threshold switching will allow an assessment of what might be possible during the act of Forming, when the threshold voltage of a selector or memory (if the latter is fabricated in its amorphous state) is reduced in some cases by a factor more than 30% from its as-fabricated value. The problem is that there have been numerous attempts to account for the threshold switching mechanism. In Part 3 of this series I will briefly explore some of threshold switching options and search for any which might be used to account for Forming.
Threshold switching: The key.
If understanding what is happening during threshold switching is the key to what might be possible during that single cycle of threshold switching associated with selector Forming, then there is a possible converse connotation: If we really understand what is happening Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 3)”
In this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.
However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.
The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”
Tom Coughlin and I are proud to announce that we have released an update of our popular emerging memory report. This report, titled Emerging Memories Ramp Up, covers all leading emerging memory technologies from PCM and 3D XPoint through MRAM and ReRAM to less-known types like carbon nanotubes and polymeric FRAMs.
Anyone who makes or uses memory chips, or who is involved in this ecosystem as an investor or tool supplier needs to read and understand this study to prepare for one of the biggest changes in the history of the chip market. The report’s wealth of information will allow companies to make strategic plans to gain a competitive edge.
The report’s forecast model has determined that the emerging memory market will grow to $20 billion by 2029 largely by displacing today’s less efficient Continue reading “Emerging Memory Report Updated”
At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline. For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).
Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array. One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.
As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”
This week the International Solid State Circuits Conference (ISSCC) was held in San Francisco. What was there? The Memory Guy will tell you!
There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).
Toshiba described a 96-layer QLC 1.33 terabit chip. Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.” Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers. They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”
Readers who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook. In this post I will share some key elements of our emerging memory forecast.
Since this is a simple blog post the forecast coverage is brief. The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.
The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.) Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications. The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.
At tighter processes flashless versions of some MCUs already ship that can Continue reading “Emerging Memories Today: Forecasting Emerging Memories”