Video: What’s Driving Tomorrow’s Semiconductors?

Samsung ForumIn early February the Samsung Strategy & Innovation Center asked for The Memory Guy to present an outlook for semiconductors as a part of the company’s Samsung Forum series.

Samsung kindly posted a video of this presentation on-line for anyone to watch.

Naturally, the presentation is memory-focused since it consists of the Memory Guy presenting to the world’s leading memory chip supplier.  Still, it also covers total semiconductor revenues and demand drivers for future non-memory technologies, as well as memory chips.

During the presentation I explained that the next few years will bring semiconductors into new applications while chips will maintain their strength in existing markets. I showed how semiconductor demand doesn’t change much over time, but that the real swing factor in chip revenues is Continue reading “Video: What’s Driving Tomorrow’s Semiconductors?”

NV Stacked Memory: Selectors and Forming (Part 1)

Ron NealeContributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.


At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline.   For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).

Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent  memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array.  One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.

As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”

Memory Sightings at ISSCC

ISSCC LogoThis week the International Solid State Circuits Conference (ISSCC) was held in San Francisco.  What was there?  The Memory Guy will tell you!

NAND Flash

There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).

Toshiba 96-layer 1Tb QLC NANDToshiba described a 96-layer QLC 1.33 terabit chip.  Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.”  Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers.  They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”

Emerging Memories Today: Forecasting Emerging Memories

Emerging Memory ParadeReaders who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook.  In this post I will share some key elements of our emerging memory forecast.

Since this is a simple blog post the forecast coverage is brief.  The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.

The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.)  Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications.  The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.

At tighter processes flashless versions of some MCUs already ship that can Continue reading “Emerging Memories Today: Forecasting Emerging Memories”

Where is Micron’s QuantX?

Micron Quantx LogoFor more than a year The Memory Guy has been fielding questions about Micron’s QuantX products.

First announced at the 2016 Flash Memory Summit, this brand name has been assigned to Micron SSDs and DIMMs that use the Intel/Micron 3D XPoint Memory.  Originally QuantX products were scheduled to ship in 2017, but Micron is currently projecting availability in 2019.  My clients wonder why there have been these delays, and why Micron is not more actively marketing this product.

The simple answer is that it doesn’t make financial sense for Micron to ship these products at this time.

Within two weeks of the first announcement of 3D XPoint Memory, at the 2015 Flash Memory Summit, I knew and explained that the technology would take two years or more to reach manufacturing cost parity with DRAM, even though Intel and Micron loudly proclaimed that it was ten times denser than DRAM.  This density advantage should eventually allow XPoint manufacturing costs to drop below DRAM costs, but any new technology, and even old technologies that are in low-volume production, suffer a decided scale disadvantage against DRAM, which sells close Continue reading “Where is Micron’s QuantX?”

Emerging Memories Today: Emerging Memory Companies

Emerging Memory ParadeMost memory industry participants view emerging memories as the eventual path of the business: There’s no doubt that today’s memory technologies will stop scaling, and that new memory technologies will need to replace today’s leading technologies both in the embedded and stand-alone spaces.  This includes DRAM, NAND flash, NOR flash, and SRAM.  Because this outlook is held by nearly everyone in the industry, all major memory manufacturers are investing in alternative memory technologies.  The leading players are researching multiple technologies at the same time.

Meanwhile, the industry outlook has allowed many university research projects and other similar efforts to gain funding to develop new memory types, spawning a large number of small single-technology companies tightly focused on one technology or another: ReRAM, MRAM, FRAM, and others, including such highly-differentiated technologies as carbon nanotubes and printable polymers.

In our Emerging Memory report Tom Coughlin and I did our Continue reading “Emerging Memories Today: Emerging Memory Companies”

Emerging Memories Today: Process Equipment Requirements

Emerging Memory ParadeSomething that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field.  This is not measured in pages, but in the topics that we cover.  For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.

All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common.  One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)

This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others.  For the most part these tools will be used for deposition and etch.  The lithography requirements will be satisfied by the tools used to pattern the metal layers.

The process flow in this figure sheds some light on the steps that Continue reading “Emerging Memories Today: Process Equipment Requirements”

Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.

Emerging Memory ParadeHere in the US we use an extremely odd expression.  If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!”  This is a very lengthy way to say: “numerous.”  (I don’t believe that ANYONE understands how that expression became a part of our vernacular!)  Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today.  There are certainly lots of them!

This post is intended to be very high-level technical description of today’s leading emerging memory technologies.  These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.

PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures.  The crystalline state has a low resistance and the amorphous state has a high resistance.  This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.

In chemistry and physics, anything with a Continue reading “Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.”

Accelerating New Memory Materials Research

Intermolecular Characterization ChartWith all the new emerging memories that are being developed there must be quite a number of test runs to study exactly how well these new technologies and materials can perform.  If a batch of 300mm wafers must be used for a single test then the cost multiplies, particularly if no other test can be run on that wafer.

Another great difficulty is that most memory manufacturers run their wafers on very high-efficiency and high-volume wafer fabs.  It is perilous and wasteful to interrupt a production process to inject a batch of test wafers.  Most fab managers would rather have a tooth pulled than to change their flow to accept an experimental lot.

What can be done to improve this situation?

Well the folks at Intermolecular, Inc. (IMI) explained to the Memory Guy that they have a solution: They have built a small fab that allows single wafers to be processed with varying parameters across a single wafer.  In this way one wafer can be used to run 36 or more different experiments all at the same time.  This is clearly more economical than having to run the experiment on 36 wafers or, even worse, 36 batches of wafers!  Intermolecular says that, while production fabs are optimized for manufacturing, their fab is optimized for materials understanding.

The firm calls itself an Continue reading “Accelerating New Memory Materials Research”

Emerging Memories Today: Understanding Bit Selectors

Emerging Memory ParadeThe previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary.  Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves.  The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology.  Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!

A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here.  It’s not complicated.

Every bit cell in a memory chip requires a selector.  This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written.  The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading “Emerging Memories Today: Understanding Bit Selectors”