Tomorrow’s Memory Technologies

Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch

Ron NealeThis is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.


Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch.  Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.

If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.

One little conundrum we must address is: Which Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation

Ron NealeThis is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.


After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of  the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.

In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper.  This means that, Continue reading

Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance

Ron NealeThis is the first of a new line-up of Memory Guy posts by Ron Neale.   In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.


In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of  PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected.  This series will investigate some of the potential reasons for this discrepancy.

Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of  greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less.  The table below Continue reading

Ron Neale To Share Posts

Ron NealeThe Memory Guy is pleased to begin publishing posts from Ron Neale.  Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.

Ron’s career has centered around phase-change memory.  He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.

Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.

Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.

Latest White Paper: New Memories for Efficient Computing

A Potpourri of Emerging MemoriesThere has been a lot of discussion in the trade press lately about new memory technologies.  This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.

But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.

Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies.  The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.

It also provides a Continue reading

Storage/Memory Hierarchy 40 Years Ago

1978 Memory/Storage HierarchyLast year I stumbled upon something on the Internet that I thought would be fun to share.  It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes.  The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency.  The vertical axis shows cost per bit.  The chart uses a log-log format: both the X and Y axes are in orders of magnitude.  This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented.  First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.”  TTL and ECL, technologies that are seldom Continue reading

Wafer Shortages and DRAM/NAND

Mark Thirsk, Linx ConsultingRecently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.

The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting.  Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.

Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies.  I asked him about this chart as well.

Here’s what Mark had to say:

“Our information is that major Continue reading

Original PCM Article from 1970

For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device.  After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.

The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron).  Intel, though, didn’t appear to have anything to share but the cover photo.

Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.

It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who has been a regular contributor to EE Times and who now also contributes blog posts to The Memory Guy.

I was astounded to discover that Continue reading

New Report Details NVDIMM Market

Objective Analysis NVDIMM Report 2017 CoverObjective Analysis has just released a new report covering the nonvolatile dual inline memory module (NVDIMM) market in detail.  This report, Profiting from the NVDIMM Market, explains the What, How, Why, & When of today’s and tomorrow’s NVDIMM products.

My readers know that I have been watching this market for some time, and that I am always perplexed as to whether to post about NVDIMMs in The Memory Guy or in The SSD Guy, since these products straddle the boundary between memory and storage.  This time my solution is to publish posts in both!

The Objective Analysis NVDIMM market model reveals that the market for NVDIMMs is poised to grow at a 105% average annual rate to nearly 12 million units by 2021.  This finding is based on a forecast methodology that has provided many of the most consistently-accurate forecasts in the semiconductor business.  This forecast, and the report itself, were compiled through exhaustive research into the technology and the events leading up to its introduction, vendor and user interviews, and briefings from standards bodies.

This 80-page in-depth analysis examines all leading NVDIMM types and forecasts their unit and revenue shipments through 2021.  Its 42 figures and 14 tables help Continue reading

Examining 3D XPoint’s 1,000 Times Endurance Benefit

3D XPoint Endurance GraphicThe Memory Guy, as a regular reader of The SSD Guy’s posts, found an interesting one that compares the endurance of Optane SSDs against that of NAND flash SSDs.  Perhaps this could provide some insight into the Intel & Micron claim that 3D XPoint Memory’s endurance is 1,000 times that of standard NAND flash, shown in the graphic to the left.

The SSD Guy post converts several different measures of SSD endurance against each other: TBW, DWPD, and GB/Day.  Definitions of these terms can be found in that post.

It occurred to me that any of these can be used to roughly gauge the relative endurance of 3D XPoint Memory against that of NAND flash.

Take DWPD for example: Drive Writes per Day.  Not only is this a measure of how many times that an SSD can be over-written every day, but it’s also an indication of the number of times that each memory cell can be overwritten.  If you know this, and if you know how long Continue reading