In this third part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
From Part 2 of this series it is very clear that only a detailed and accurate description of threshold switching will allow an assessment of what might be possible during the act of Forming, when the threshold voltage of a selector or memory (if the latter is fabricated in its amorphous state) is reduced in some cases by a factor more than 30% from its as-fabricated value. The problem is that there have been numerous attempts to account for the threshold switching mechanism. In Part 3 of this series I will briefly explore some of threshold switching options and search for any which might be used to account for Forming.
Threshold switching: The key.
If understanding what is happening during threshold switching is the key to what might be possible during that single cycle of threshold switching associated with selector Forming, then there is a possible converse connotation: If we really understand what is happening Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 3)”
This week’s HotChips conference featured a concept called “Processing in Memory” (PIM) that has been around for a long time but that hasn’t yet found its way into mainstream computing. One presenter said that his firm, a French company called UPMEM, hopes to change that.
What is PIM all about? It’s an approach to improving processing speed by taking advantage of the extraordinary amount of bandwidth available within any memory chip.
The arrays inside a memory chip are pretty square: A word line selects a large number of bits (tens or hundreds of thousands) which all become active at once, each on its own bit line. Then these myriad bits slowly take turns getting onto the I/O pins.
High-Bandwidth Memory (HBM) and the Hybrid Memory Cube (HMC) try to get past this bottleneck by stacking special DRAM chips and running Continue reading “UPMEM Processor-in-Memory at HotChips Conference”
In this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.
However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.
The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”
Tom Coughlin and I are proud to announce that we have released an update of our popular emerging memory report. This report, titled Emerging Memories Ramp Up, covers all leading emerging memory technologies from PCM and 3D XPoint through MRAM and ReRAM to less-known types like carbon nanotubes and polymeric FRAMs.
Anyone who makes or uses memory chips, or who is involved in this ecosystem as an investor or tool supplier needs to read and understand this study to prepare for one of the biggest changes in the history of the chip market. The report’s wealth of information will allow companies to make strategic plans to gain a competitive edge.
The report’s forecast model has determined that the emerging memory market will grow to $20 billion by 2029 largely by displacing today’s less efficient Continue reading “Emerging Memory Report Updated”
With Intel’s Cascade Lake rollout last month came with a co-introduction of 3D XPoint Memory in a DIMM form factor, the Optane DIMM that had been promised since the first introduction of 3D XPoint Memory in mid-2015. A lot of benchmarks were provided to make the case for using Optane DIMMs (formally known as the Intel Optane DC Persistent Memory), but not much was said about the pricing, except for assertions that significant savings were possible when Optane was used to replace some of the DRAM in a large computing system.
So… How much does it cost? Well certain technical reports in resources like Anandtech probed sales channels to see what they could find, but The Memory Guy learned that the presentations Intel made to the press in advance of the Cascade Lake rollout contained not only prices for the three Optane DIMM densities (128, 256, & 512GB), but also provided the prices of the DRAM DIMMs that they were being compared against. I’ll get to that in a moment, but first let’s wade through the fundamentals of Intel’s Optane pricing strategy to understand why Intel has needs to price it the way that it has.
In Objective Analysis’ report on 3D XPoint Memory, and in several presentations I have Continue reading “Intel’s Optane DIMM Price Model”
With the release of its Cascade Lake family of processors today (formally called the “2nd Generation Intel Xeon Scalable processor”) Intel disclosed more details about its Optane DIMM, which has been officially named the “Intel Optane DC Persistent Memory.” This DIMM’s architecture is surprisingly similar to an SSD, even to the point of its having error correction and encryption!
The Memory Guy doesn’t generally cover SSDs, but I do cover DIMMs, so this is one of those posts that I could have put into either of my blogs: The Memory Guy or The SSD Guy. I have decided to put it here with the hopes that it will be easier for members of the memory community to find.
The internal error correction, the encryption, and the fact that 3D XPoint Memory wears out and must use wear leveling, all cause the Optane DIMM’s critical timing path to be slower than the critical path in a DRAM DIMM, rendering the Optane DIMM unsuitable for code execution. This, and the fact that XPoint writes are slower than its reads, all help to explain why an Optane DIMM is never used as the only memory in a system: there is always a DRAM alongside the Optane DIMM to provide faster Continue reading “What’s Inside an Optane DIMM?”
The Memory Guy today became aware of a significant breakthrough in magnetic memory technologies (MRAM) that could prove to be a big bonus for mobile applications. These memories could be used to generate power as well as to store data.
Scientists have only recently become aware of an oversight stemming from the fact that nearly all spin magnetics research has been performed in the northern hemisphere. Just as the water in a drain rotates counterclockwise in the northern hemisphere but clockwise in the southern hemisphere, the Coriolis Effect dictates that magnetic spin has the opposite sense above the equator as below.
This surprise finding was made when researchers from Stüdpfalz University of Blindman’s Bluff, Iowa, brought samples of an STT MRAM they had developed to the Townsville City Metropolitan University in Queensland, Australia, where researchers have been producing similar magnetic memories below the equator. Until that moment neither team had thought to question the Continue reading “MRAMs to Power Cell Phones”
In early February the Samsung Strategy & Innovation Center asked for The Memory Guy to present an outlook for semiconductors as a part of the company’s Samsung Forum series.
Samsung kindly posted a video of this presentation on-line for anyone to watch.
Naturally, the presentation is memory-focused since it consists of the Memory Guy presenting to the world’s leading memory chip supplier. Still, it also covers total semiconductor revenues and demand drivers for future non-memory technologies, as well as memory chips.
During the presentation I explained that the next few years will bring semiconductors into new applications while chips will maintain their strength in existing markets. I showed how semiconductor demand doesn’t change much over time, but that the real swing factor in chip revenues is Continue reading “Video: What’s Driving Tomorrow’s Semiconductors?”
In this first post of a five-part series contributor Ron Neale analyzes selector technologies presented by CEA Leti at the 2018 IEDM conference last December.
At the close of last year the IEDM maintained its long-standing reputation for offering across-the-board the right focus at the right time on important and key parts of the electronic device discipline. For those with an interest in the future of stacked or 3D NV-memory arrays there were a number of important papers and presentations on a variety of thin film memory selectors or matrix isolation devices (MIDs).
Important, because as the move towards stacked memory arrays for storage class memory (SCM) and persistent memory (PM) applications gains momentum, the thin film selector may be the device which is key in determining the performance and reliability for a number of different types of NV memory arrays or even the very existence of that type of memory array. One of the important and poorly understood variables in the mix is the selector forming voltage and the structural changes which lead from it to the operating device threshold voltage which, in my view needs a lot more by way of detailed understanding.
As the memory array moves into Continue reading “NV Stacked Memory: Selectors and Forming (Part 1)”
This week the International Solid State Circuits Conference (ISSCC) was held in San Francisco. What was there? The Memory Guy will tell you!
There were three NAND flash papers, one each from Toshiba, Samsung, and Western Digital Corp. (WDC).
Toshiba described a 96-layer QLC 1.33 terabit chip. Like the chip that Toshiba presented last year, this one uses CUA, which Toshiba calls “Circuit Under Array” although Micron, who originated the technology, says that CUA stands for “CMOS Under Array.” Toshiba improved the margins between the cells by extending the gate threshold ranges below zero, a move that forced them to re-think the sense amplifiers. They also implemented a newer, faster, lower-error way to Continue reading “Memory Sightings at ISSCC”