Contributor Ron Neale joins us again to review a paper delivered at last December’s IEDM conference by John Moores & Cambridge Universities, IMEC, and the University of Wuhan. While the main focus of the paper is on PCM endurance improvements, it also provides some new inputs, which, with some suggested additions of Neale’s own, might now provide a unified explanation of threshold switching in the chalcogenides. Neale includes discussions of these new ideas with one of the paper’s authors.
One of the most interesting papers at the recent IEDM was presented by a team at: John Moores University Liverpool, and Cambridge University, UK, IMEC, Belgium and the University of Wuhan, China. As its title makes clear, this research has an important target of Continue reading “NVM Selectors: A Unified Explanation of Threshold Switching”
In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of Continue reading “Chalcogenide Selectors and Oxide Memory Move Towards 1Gbit”
Ron Neale returns to The Memory Guy blog to discuss a “Universal Law” about memory elements and selectors that was presented by CEA Leti at the IEEE’s 2019 IEDM conference last December.
At IEDM 2019 D. Alfaro Robayo et al presented a paper titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration that had a rather interesting claim of a “Universal Law”. It is possible that some links to the past might help to provide an explanation for Continue reading “Observations on the “Universal Law” for NV Memory Cells”
In this final part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing on the nature of the mystery of Forming and a number of the many unanswered questions.
Any search for Forming-Free structures might find some help in the article by Antonin Verdy of Leti titled: Optimized Reading Window for Crossbar Arrays Thanks to Ge-Se-Sb-N-based OTS Selectors. This article also Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 5)”
In this fourth part of a five-part series, contributor Ron Neale continues his analysis of selector technologies, focusing on the nature of the mystery of Forming and a number of the many unanswered questions.
From the discussion and investigations outlined in the earlier parts of this series, there would appear to be a number of options to explain selector Forming, where on the first switching event the threshold switching voltage Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 4)”
Almost one year ago Tom Coughlin and The Memory Guy presented the findings of our first emerging memories report at the Storage Networking Industry Association’s (SNIA) Storage Developers Conference (SDC). The podcast of this presentation has just been made available on the SNIA website.
In the podcast, titled “The Long and Winding Road to Persistent Memories,” Tom and I reviewed leading emerging memory technologies as we had surveyed them for our report.
This is a highly visual presentation, so I would recommend following along with the slides, which can also be downloaded from the SNIA SDC website at HERE. That same page combines the slides and the podcast into a video, so if you’re able to, it might be a good idea to watch the video. If you’re driving as your listening to it, though, then please use the podcast instead!
In the time since that podcast was recorded Tom and I have updated the report to a 2019 edition, which can be Continue reading “Podcast: Storage Developer Conference 2018 – Emerging Memories”
In this third part of a five-part series, contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
From Part 2 of this series it is very clear that only a detailed and accurate description of threshold switching will allow an assessment of what might be possible during the act of Forming, when the threshold voltage of a selector or memory (if the latter is fabricated in its amorphous state) is reduced in some cases by a factor more than 30% from its as-fabricated value. The problem is that there have been numerous attempts to account for the threshold switching mechanism. In Part 3 of this series I will briefly explore some of threshold switching options and search for any which might be used to account for Forming.
Threshold switching: The key.
If understanding what is happening during threshold switching is the key to what might be possible during that single cycle of threshold switching associated with selector Forming, then there is a possible converse connotation: If we really understand what is happening Continue reading “NV Memory Selectors: Forming the Known Unknowns (Part 3)”
In this second part of a five-part series contributor Ron Neale continues his analysis of selector technologies focusing the nature of the mystery of Forming and a number of the many unanswered questions.
Thin film selectors, or memory matrix isolation devices, based on chalcogenide glasses, would appear to be the devices of choice as non-volatile memory arrays move towards 3D stacked structures. Considerable progress has been made in finding selector compositions which can be doped to provide a suitable level of structural stability required for the NV memory array application. These were discussed in the first part of this series.
However, there is one known unknown in relation to this type of selector and it is the need for Forming, with the unknown being the physical nature of the changes which occur within the device as a result of the Forming process and any implications those changes might have on reliability and performance. The outward manifestation of Forming is a change in threshold voltage from an initial value to some lower more constant operating value. Not just a minor threshold voltage change but a significant one, a reduction of the order 36% in some cases.
The diagram below illustrates Continue reading “NV Stacked Memory Selectors: Forming the Known Unknowns (Part 2)”
Tom Coughlin and I are proud to announce that we have released an update of our popular emerging memory report. This report, titled Emerging Memories Ramp Up, covers all leading emerging memory technologies from PCM and 3D XPoint through MRAM and ReRAM to less-known types like carbon nanotubes and polymeric FRAMs.
Anyone who makes or uses memory chips, or who is involved in this ecosystem as an investor or tool supplier needs to read and understand this study to prepare for one of the biggest changes in the history of the chip market. The report’s wealth of information will allow companies to make strategic plans to gain a competitive edge.
The report’s forecast model has determined that the emerging memory market will grow to $20 billion by 2029 largely by displacing today’s less efficient Continue reading “Emerging Memory Report Updated”
With Intel’s Cascade Lake rollout last month came with a co-introduction of 3D XPoint Memory in a DIMM form factor, the Optane DIMM that had been promised since the first introduction of 3D XPoint Memory in mid-2015. A lot of benchmarks were provided to make the case for using Optane DIMMs (formally known as the Intel Optane DC Persistent Memory), but not much was said about the pricing, except for assertions that significant savings were possible when Optane was used to replace some of the DRAM in a large computing system.
So… How much does it cost? Well certain technical reports in resources like Anandtech probed sales channels to see what they could find, but The Memory Guy learned that the presentations Intel made to the press in advance of the Cascade Lake rollout contained not only prices for the three Optane DIMM densities (128, 256, & 512GB), but also provided the prices of the DRAM DIMMs that they were being compared against. I’ll get to that in a moment, but first let’s wade through the fundamentals of Intel’s Optane pricing strategy to understand why Intel has needs to price it the way that it has.
In Objective Analysis’ report on 3D XPoint Memory, and in several presentations I have Continue reading “Intel’s Optane DIMM Price Model”