Emerging Memories Today: Understanding Bit Selectors
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves. The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology. Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!
A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here. It’s not complicated.
Every bit cell in a memory chip requires a selector. This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written. The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading
Emerging Memories Today: Why Emerging Memories are Necessary
Non-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred. Why is that, and why should anything change?
This is a question that The Memory Guy is often asked. The answer is relatively simple.
Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes. In fact, before the middle 1980s, logic and memory processes were identical. It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.
Even so, memory processes and logic processes are more similar than different. This synergy between memory and logic continues to reduce the process development cost for both memories and logic.
Emerging memories depart from Continue reading
Emerging Memories Today: New Blog Series
There’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own. Today it appears that their opportunity is very near.
Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue. But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies. Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing. It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.
This post introduces a Continue reading
Monatomic PCMs: A New Direction
[The following is a guest post written by Ron Neale.]
Until now designers of PCM devices have tried to make PCM meet their expectations by experimenting with an almost infinite number of possible multi-element glass compositions, in order to tinker with or emphasise a particular composition-related device characteristic. The apparent advantage of this great variety of materials comes with the baggage of reliability and performance-compromising element separation, driven by the forces of electro-migration, electrostatic effects and phase separation.
Is it possible to cast aside the problems of the multi-element PCM compositions and look at the possibility of monatomic PCMs? For a team at IBM, Zurich and Aachen University the answer is an unequivocal “Yes!” and recently they have published details of the remarkable progress they have made with amorphous antimony (Sb), as an initial candidate element. This research was published in a June 2018 paper in Nature Materials Letters titled: Monatomic phase change memory, by Martin Salinga et al, IBM and Aachen University).
A difficulty faces those venturing in this new direction: While it is possible to bring many elements to the amorphous state, they very quickly crystallize at room temperature and higher. The IBM researchers used simulations to find that the keys to obtaining a stable amorphous state is to control the quenching rate and the volume of the sample. That part of the antimony research is underpinned by some very impressive simulations that use only about 200 atoms.
Here’s the issue that this approach Continue reading
Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane
This is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.
I want, in this final part, to focus on its possible implications for commercial PCM products.
When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM). Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.
The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs. In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance. (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)
As the calculated Continue reading
Making Sense of Intel & Micron’s XPoint Breakup
On Monday, July 16, Intel and Micron announced the termination of the two companies’ 3D XPoint Memory development efforts. The companies will complete development of the second-generation product after which the IMFT Lehi, Utah facility will continue to manufacture the product but the two companies will no longer co-develop new versions of the 3D XPoint Memory.
Most readers haven’t been watching this business as carefully as The Memory Guy, and are puzzled by the move. I will share what I know in an attempt to make the decision a little clearer.
Three years ago in July 2015 the two companies held an event to launch 3D XPoint Memory technology. This upcoming technology would be 1,000 times faster than flash, and provide 1,000 times the endurance, on a chip that was 10 times as dense as “Standard Memory,” which everyone was to infer was DRAM. This last implied that the technology would sell for a lower price than DRAM, and that’s the most important way that a technology that’s slower than DRAM can gain acceptance in a Continue reading
Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch
This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.
Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.
If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.
One little conundrum we must address is: Which Continue reading
Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation
This is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.
After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.
In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper. This means that, Continue reading
Extending the Write/Erase Lifetime of Phase Change Memory: Part 1- PCM Element Separation and Endurance
This is the first of a new line-up of Memory Guy posts by Ron Neale. In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.
In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected. This series will investigate some of the potential reasons for this discrepancy.
Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less. The table below Continue reading
Ron Neale To Share Posts
The Memory Guy is pleased to begin publishing posts from Ron Neale. Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.
Ron’s career has centered around phase-change memory. He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.
Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.
Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.
