Something that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field. This is not measured in pages, but in the topics that we cover. For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.
All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common. One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)
This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others. For the most part these tools will be used for deposition and etch. The lithography requirements will be satisfied by the tools used to pattern the metal layers.
The process flow in this figure sheds some light on the steps that Continue reading “Emerging Memories Today: Process Equipment Requirements”
Here in the US we use an extremely odd expression. If there are multiple varieties of an item we commonly say: “There are more of them than you can shake a stick at!” This is a very lengthy way to say: “numerous.” (I don’t believe that ANYONE understands how that expression became a part of our vernacular!) Although The Memory Guy isn’t normally seen shaking a stick, I find it an apt way to describe the numerous new memory technologies that are being pioneered today. There are certainly lots of them!
This post is intended to be very high-level technical description of today’s leading emerging memory technologies. These are excerpts of the in-depth descriptions that can be found in our recently-released report: Emerging Memories Poised to Explode.
PCM: Also known as PRAM, Phase-Change Memory technology is based upon a material that can be either amorphous or crystalline at normal ambient temperatures. The crystalline state has a low resistance and the amorphous state has a high resistance. This is controlled by melting the bit cell by passing a current though it and then allowing it to cool at different rates.
In chemistry and physics, anything with a Continue reading “Emerging Memories Today: The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.”
With all the new emerging memories that are being developed there must be quite a number of test runs to study exactly how well these new technologies and materials can perform. If a batch of 300mm wafers must be used for a single test then the cost multiplies, particularly if no other test can be run on that wafer.
Another great difficulty is that most memory manufacturers run their wafers on very high-efficiency and high-volume wafer fabs. It is perilous and wasteful to interrupt a production process to inject a batch of test wafers. Most fab managers would rather have a tooth pulled than to change their flow to accept an experimental lot.
What can be done to improve this situation?
Well the folks at Intermolecular, Inc. (IMI) explained to the Memory Guy that they have a solution: They have built a small fab that allows single wafers to be processed with varying parameters across a single wafer. In this way one wafer can be used to run 36 or more different experiments all at the same time. This is clearly more economical than having to run the experiment on 36 wafers or, even worse, 36 batches of wafers! Intermolecular says that, while production fabs are optimized for manufacturing, their fab is optimized for materials understanding.
The firm calls itself an Continue reading “Accelerating New Memory Materials Research”
The previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary. Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves. The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology. Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!
A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here. It’s not complicated.
Every bit cell in a memory chip requires a selector. This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written. The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the Continue reading “Emerging Memories Today: Understanding Bit Selectors”
Non-silicon memory technologies have been studied for about as long as have silicon-based technologies, but the silicon technologies have always been preferred. Why is that, and why should anything change?
This is a question that The Memory Guy is often asked. The answer is relatively simple.
Silicon memory technologies benefit from the fact that they have always been manufactured on process technologies that are nearly identical to those used to produce CMOS logic, and can therefore take advantage of the advancements that are jointly developed for both memory and logic processes. In fact, before the middle 1980s, logic and memory processes were identical. It wasn’t until then that the memory market grew large enough (over $5 billion/year) that it could support any additional process development on its own.
Even so, memory processes and logic processes are more similar than different. This synergy between memory and logic continues to reduce the process development cost for both memories and logic.
Emerging memories depart from Continue reading “Emerging Memories Today: Why Emerging Memories are Necessary”
There’s never been a more exciting time for emerging memory technologies. New memory types like PCM, MRAM, ReRAM, FRAM, and others have been waiting patiently, sometimes for decades, for an opportunity to make a sizeable markets of their own. Today it appears that their opportunity is very near.
Some of these memory types are already being manufactured in volume, and the established niches that these chips sell into can provide good revenue. But the market is poised to experience a very dramatic upturn as advanced logic processing nodes drive sophisticated processors and ASICs to adopt emerging persistent memory technologies. Meanwhile Intel has started to aggressively promote its new 3D XPoint memory for use as a persistent (nonvolatile) memory layer for advanced computing. It’s no wonder that SNIA, JEDEC, and other standards bodies, along with the Linux community and major software firms are working hard to implement the necessary standards and ecosystems to support widespread adoption of the persistent nature of these new technologies.
This post introduces a Continue reading “Emerging Memories Today: New Blog Series”
[The following is a guest post written by Ron Neale.]
Until now designers of PCM devices have tried to make PCM meet their expectations by experimenting with an almost infinite number of possible multi-element glass compositions, in order to tinker with or emphasise a particular composition-related device characteristic. The apparent advantage of this great variety of materials comes with the baggage of reliability and performance-compromising element separation, driven by the forces of electro-migration, electrostatic effects and phase separation.
Is it possible to cast aside the problems of the multi-element PCM compositions and look at the possibility of monatomic PCMs? For a team at IBM, Zurich and Aachen University the answer is an unequivocal “Yes!” and recently they have published details of the remarkable progress they have made with amorphous antimony (Sb), as an initial candidate element. This research was published in a June 2018 paper in Nature Materials Letters titled: Monatomic phase change memory, by Martin Salinga et al, IBM and Aachen University).
A difficulty faces those venturing in this new direction: While it is possible to bring many elements to the amorphous state, they very quickly crystallize at room temperature and higher. The IBM researchers used simulations to find that the keys to obtaining a stable amorphous state is to control the quenching rate and the volume of the sample. That part of the antimony research is underpinned by some very impressive simulations that use only about 200 atoms.
Here’s the issue that this approach Continue reading “Monatomic PCMs: A New Direction”
This is Part 4 of a series contributed by Ron Neale to the Memory Guy blog, in which Ron looks into some important detailed analytical work by a joint team at IBM and Yale University which might point to the way of achieving improved PCM endurance.
I want, in this final part, to focus on its possible implications for commercial PCM products.
When Intel and Micron first introduced 3D XPoint Memory the companies claimed that it would be 1,000 times as fast as flash memory with 1,000 times the endurance at ten times the density of standard memory (meaning DRAM). Now that Intel’s XPoint-based Optane SSDs have been released and their specifications are public we can estimate what the technology’s endurance might be.
The table below, explained in another Memory Guy blog post, gives estimates of best-case endurance for the cells in the XPoint memory in Optane SSDs. In other words, with a sophisticated enough controller, good DRAM buffering, and overprovisioning, all of which are techniques commonly used to extend the life of the media in a NAND flash SSD, the cell lifetime could be significantly lower than that shown in the last column of the table and the SSD would still provide the specified endurance. (These techniques are explained in detail in an SSD Guy blog post series for anyone who is interested in understanding them.)
As the calculated Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 4 – The Possible Implications for 3D XPoint and Optane”
On Monday, July 16, Intel and Micron announced the termination of the two companies’ 3D XPoint Memory development efforts. The companies will complete development of the second-generation product after which the IMFT Lehi, Utah facility will continue to manufacture the product but the two companies will no longer co-develop new versions of the 3D XPoint Memory.
Most readers haven’t been watching this business as carefully as The Memory Guy, and are puzzled by the move. I will share what I know in an attempt to make the decision a little clearer.
Three years ago in July 2015 the two companies held an event to launch 3D XPoint Memory technology. This upcoming technology would be 1,000 times faster than flash, and provide 1,000 times the endurance, on a chip that was 10 times as dense as “Standard Memory,” which everyone was to infer was DRAM. This last implied that the technology would sell for a lower price than DRAM, and that’s the most important way that a technology that’s slower than DRAM can gain acceptance in a Continue reading “Making Sense of Intel & Micron’s XPoint Breakup”
This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.
Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.
If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.
One little conundrum we must address is: Which Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch”