CeRAM Moves Front and Center on the NV Memory Stage

Photo of Ron Neale, Renowned Phase-Change Memory ExpertIn this post contributor Ron Neale shares a close look at the new memory announced today by Arm spin-off Cerfe Labs.  He provides insight into the operation and composition of this technology which originated at Symetrix, a company that has previously developed FRAM technologies licensed to major semiconductor and capacitor manufacturers.


While many companies seek to offer a nonvolatile (NV) alternative to Flash, with varying degrees of success, something new called a correlated electron memory (CeRAM) has entered the fray in the form of a brand-new start-up company called Cerfe Labs.  The company, named for Research into Correlated Electron and Ferro Electric devices, is located in Austin, Texas and San Jose, California and was established as a spin-off from ARM-Softbank.

While the company may be new, the memory is not new.  Those of us who follow NV memory have for some years known about CeRAM and in particular followed the work of Professor Carlos Paz de Araujo at University of Colorado, Colorado Springs. The CeRAM and the technology on which it is based is his baby.  It has been waiting in the wings, but now it appears its day may have come.

In recent years CeRAM memory technology has been investigated by a number of companies and licensees, with the latest being ARM and Symetrix.  These two companies have had it under investigation for some time, with imec involved in some of the processing activity.  It would appear that sufficient progress has now been made for a new start-up company to ready the technology for a move into a mainstream fabrication facility.


The initial results of processing CeRAM on 300mm wafers has been successfully completed.  Devices processed in a number of different and separate fabrication facilities have produced CeRAM cells with the same switching characteristics.  The latter is a very important multiple third-party confirmation that CeRAM switching is not some one-time laboratory observation.

It may be some months or a year or so away from a new fully-proven CeRAM memory array product or a fully fledged process from Cerfe Labs or its licensees.  Still, there are some very attractive characteristics of the technology which will act as driving forces.  The wisest course might be to first target small niche applications where unique CeRAM features can be exploited and to leave the high-density arrays to the licensees.

Characteristics & Composition

The I -V characteristics of the CeRAM cell are shown below.  Two very important features that are key to its success are the low switching voltage, so far, the best achieved is sub 0.6 volts, and the low switching current densities.  Even more importantly, the switching between the two memory states does not appear to involve melting or filaments, it is claimed as a bulk switching effect.I-V curves for CeRAM bit cell and insert electron microscope view of the cell's profileThe memory cell uses what appear to be some of the lowest switching voltages and current densities of any of the competing emerging memory technologies, with no requirement for forming.

The name CeRAM derives from the fact that in conventional semiconductors, like silicon, electrons or holes are considered to be uncorrelated as they move around, in that they do not interfere or interact with each other.  In a CeRAM memory material, the fact that carriers do interact with each other allows the two states of conduction required for a binary memory to be realised.

The memory materials are transition metal oxides NiO, TiO and YtTiO.  To date of those NiO has received the most attention.  However, a thin film of NiO is an insulator, although received wisdom says it should be a metal, and neither will get you a memory.  It will certainly suffer dielectric breakdown like any dielectric if enough voltage is applied.

The secret is controlled doping using Carbonyl as a doping agent.  Carbonyl allows the NiO structure (and now other transition metal oxides) to be modified through the inclusion of carbon.

The doping process is capable of producing NiO films with a complete range of characteristics ranging from an electrical insulator to conductor, with some in-between levels which can switch between two stable states.  For memory devices the NiO is doped so it starts life as a conductor which can then be electrically switched between its conducting and insulating state.

The current density for switching is low (of the order 2 x10^5 Amps/sq cm).  Low, that is, compared with some other emerging NV memory technologies, so the damaging effects of electromigration or melting are unlikely to create any endurance or reliability problems.

Bulk Switching

One measure of the evidence of bulk switching is that current density remains constant as the device structures are scaled.  From early research devices with micron-sized dimensions (5 x5µm) to the present nanometric-sized devices there has been some increase in current density.  This should not be construed as evidence that conduction mechanisms of filaments or grain boundary decoration are at work.

Representatives of Cerfe Labs inform us that “The current density results from device diameters from 150nm to 47nm are consistent with a bulk switching mechanism and there is no indication they are anywhere near a dimensional limit.”

Those trying to make the case for filaments against bulk switching have to deal with the fact that CeRAM devices are fabricated in what Cerfe Labs call the “Born On” or conducting state. If bulk switching is not a correct interpretation then the initial switching event from the LRS to HRS state would leave a field of conducting material around any filament. The fact that there is no difference between the initial as-born switching event and subsequent ones, each of which would require different voltage and currents, shows that CeRAMs do not require Forming, and this rules out some sort of complex mixed type of bulk and filament switching.

In addition, the new company has seen no evidence of filaments from XPS and AFM scans, and (X-ray) band structure investigation underway.

There are a number of variables, such as doping levels and processing variables which can be used to advantage and could account for differences in current density for devices of different areas.

Some will try to make a case in favour of filament over bulk switching for carbon-doped TMOs, or even for some type of complex mixed filament/bulk mechanism, for example like that which occurs in phase change memory (PCMs).  Advocates of such alternatives must address the following problem.

If a filament is Formed on the first RESET pulse how does the conducting material around that filament get RESET to the high resistance state?  In PCMs the transition from the SET to the RESET state involves melting (Temp~600°C) the whole of the volume of material, or alternatively the use of a high-voltage Forming pulse when PCMs are fabricated in the amorphous state.

CeRAM devices are fabricated in the conducting state and in order to melt the whole volume of material, with a melting temperature of about 1900°C, would take a very large forming pulse. Without any evidence of a much larger Forming pulse for CeRAMs how could that occur?

The melting temperature of 1900° also negates any suggestion that the conducting material could be removed by a technique similar to that used in the early days for large area PCMs where the material could be reset from the crystalline to the amorphous state by molten filament-by-filament reset pulse sequence.

As far as I am aware at this time the initial LRS to HRS transition for a CeRAM in the as-fabricated or born-on state only requires a single pulse the same as subsequent ones.

For some the “N” type, negative resistance might suggest bulk switching of the formation planar domains.  This argument might be countered by the fact that the return to the conducting state is “S” type negative resistance, which would suggest filaments are involved.  The fact that there is evidence of bulk tunnelling in the I-V characteristics before switching from the high-resistance state mitigates against any case for filaments during the return to the conducting state.


A summary of the best characteristics to-date are provided in the table below:

Feature Value
On-to-off resistance ratio (HRS/LRS) 100 (500 with early devices)
Switching time 2ns (Test equipment limited)
Temperature coefficients of switching voltages Close to zero over the range
25°C to 115°C
Elevated temperature data retention 24 hours at 400°C: no change
Write/erase endurance Results for memory arrays will be forthcoming*
TMO film processing Spin-on slurry, ALD or PVD
Electrode materials Platinum (Pt) or Iridium (Ir) **
Active materials Carbon doped Ni, or HfO2, or YTiO3

* The rapid switching time and self-capacitance of large area devices result in large and damaging (i = C dV/dt) currents which compromise endurance tests.
** A triple-layer sandwich of memory material with layers of non-switching conducting thin metal oxide (TMO) contacting the electrodes is an option which would allow most conductor materials common in semiconductor fabrication to be used.

Material engineering with the possibility of using the trade-off between carbon doping, resistance thickness and threshold voltage will lead to the optimum device structure and characteristics.

The Switching Mechanism

Two names are used interchangeably to describe the CeRAM switching mechanisms, they are “strongly correlated electron (SCE)” or “orbit switching”.

Unlike conventional single-crystal silicon, for CeRAM the band gap changes for each switching event, without at the same time causing any change in the physical structure.  Those trained in what we call conventional solid electronics might find this a bit strange and may even require a new electronics knowledge baseline.

When the materials are in the insulating state they are described as charge-transfer insulators (CTIs) because the band gap that separates the valence and conduction bands is the result of charge transfer.  The charges being transferred are electrons changing orbits or, more accurately, becoming localised.

In the insulating state the repulsion between an ion with localised electrons and any other electrons is responsible for the band gap and this band gap cannot be bridged by low-energy electrons.

When sufficient voltage and current are applied to the carbon-doped TMO it is possible to dislodge the localised electron and this causes the band gap to disappear to make the valance and conduction bands overlap.  From then on, the conducting electrons, in effect, screen any repulsive effects from ions without a localized electron.  The material becomes a metallic-like conductor as illustrated below.

Band gap diagrams of set (left) and reset (right) statesProviding that the devices are only subjected to low voltages and currents, the two resistance states are permanent.  In the conducting state, without sufficient voltage applied, electron screening prevents a return to the insulating state.

In contrast, the best models of threshold switching in PCM require some small ion movement, which is facilitated by the amorphous structure.  PCM’s amorphous-to-crystalline phase change involves a massive band gap change and a significant structural change.  For the CeRAM the structure remains fixed and only electrons change position.  Charge transfer is the name of the game.

The carbon doping of the CeRAM materials replaces a nickel atom with a carbon atom in the cubic crystal structure.  This process has much in common with substitutional doping of say single-crystal silicon and band theory.  The important difference is the materials can be deposited as thin films.

In the long term, thin-film deposition offers the possibilities that CeRAM might be used in 3D stacked memory array structures like Intel’s Optane with the tempting possibility the carbon doped TMOs could be slotted straight into Intel’s Optane to replace 3D XPoint memory.  Even without that flight of fancy, in order for Intel to move from Optane’s two-stack memory configuration to the promised future higher stack counts will require a memory device which does not involve high current density and high temperature melting.  CeRAM might be the answer. For the moment let’s leave that to Intel.

Astute readers may have noticed the slight taper in the device structure shown in the micrograph inset in this post’s first graphic.  The taper is not some feature of design, it is there because the CeRAM fabrication used existing ReRAM and MRAM processing facilities. The CeRAM’s films were, in effect, the only change.

This is a sign that the road ahead for Cerfe Labs may not be as arduous or take as long as it has for NV competitors who have gone before.  While we are familiar with the term: “Drop-in Replacements” at the device level, CeRAM might now be considered as a drop in replacement for other NV memory types at the fabrication level.

We wish the founders every success with their new company and hope they receive all the support and attention that CeRAM technology now deserves.  I personally look forward the first generation of CeRAM memory products.


CeRAM gains ARM’s attention, Ron Neale, EE Times, 2014


The third through tenth paragraphs of the section “Bulk Switching” have been added to the original post a few days after publication (on October 5) to clarify and avoid any possible misunderstandings with the original post.

4 thoughts on “CeRAM Moves Front and Center on the NV Memory Stage”

  1. Beautiful Article. It is very clear. I wish I could explain CeRAM in such a simple manner. Regards, Carlos Paz de Araujo.

  2. Hi Ron,
    Great article.
    What similarities, if any, do you see between CeRAM and the correlated memory from 4DS?

    1. Steven The 4DS memory is a very interesting device and as far as I am aware still remains active and competitive in the non-volatile emerging memory race, without as yet any memory products to its name. The 4DS memory device is formed from metal oxide hetro-junction (MOHJO) based on thin films of PrCaMnO3 and is clearly positioned as an interface device rather than as a bulk switching device. Perhaps a more important differentiating feature is that the 4DS memory requires bipolar operation, while the CeRAM is a unipolar operated device. This gives strong support for bulk switching with, in addition, the need for forming in the case of the 4DS memory.
      Both would be expected to scale with constant current density. In my league table of desirability, bulk switching based on: Mott-Hubbard transitions, correlation effects, charge transfer band gaps, orbit switching or by whatever name you chose, gets preference over those which require even a small amount of atomic, ion or oxygen vacancy movements.
      However, your question raises an important point and takes us beyond the new paragraphs just added to my article, where I have tried to deal with a comment made elsewhere suggesting that CeRAMs are filament based. Is it possible the CeRAM is itself an interface device? Based on the evidence, my answer would to that question would be No. I find it difficult to conceive of an interface device which would not require bipolar operation, although it might just be possible to make a short endurance device. In their pre-launch interviews the representatives of Cerfe Labs stated (in response to my questions on the subject of using different electrode materials) that when they tried Ti, the same material used by 4DS, surface films caused problems. The only surface effect might be an initial domain of switched material, formed parallel the electrode before propagating into the bulk. “N” negative resistance-like.
      To finish let me try an anticipate the next question, which I alluded to in passing in my article: Could the CeRAM mechanism be the result of grain boundary decoration, pseudo bulk, or if you like, many nano ReRAMs in parallel? Could it be something along the lines of an IBM memory called the CoxRAM which also used Carbon doping, although in their case, using SiO, the memory effect was based on an oxidation- reduction mechanism. Without a need for bipolar operation, I don’t think so.

  3. Regarding IBM’s COxRAM work, mentioned in my comment above, since I added my comment I have heard by email from a representative of IBM “We have put this effort on hold due to the limited cycling endurance. For what our researchers want to do in the space of storage class memory and neuromorphic computing, the endurance was not good enough.”

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