In this post contributor Ron Neale takes a very deep look into a new paper published by Symetrix, Cerfe Labs and university researchers which provides fresh insights to the inner workings of CeRAM (Correlated electron RAM), an innovative class of non-volatile memory, where carbon doping of nickel oxide NiO leads to a new type of electronics based electron interaction. With the recently-disclosed material as background, he then adopts the position of Devil’s Advocate to explore alternative views of the memory switching mechanism and to test the proposition that CeRAM is not simply another kind of ReRAM.
A new and recently published paper in APL Materials  by a team from the University of Colorado, Symetrix Corporation, Cerfe Labs, The Katholieke University Belgium, Federal University of Rio de Janerio Brazil, and the University of Colorado and more recently  have provided us with some important new more detailed insights into the operation and performance of the Correlated electron Random Access Memory (CeRAM).
To support earlier claims, the publication provides some previously-unseen new data in the form of the electronic, photoconductive and structural characteristics of new materials. It also provides a very detailed theoretical analysis which accounts for the universal nature of the non-volatile memory effect in carbon doped transitional metal oxides, with new materials added to the nickel oxide (NiO) of the earlier work. Here, after a review of these new disclosures, I will explore some of the problem areas.
The CeRAM is based on the discovery and pioneering work of Prof Carlos de Paz Araujo of University of Colorado and his colleagues Chris Williams and Jolanta Celinska, and has been in a state of development for a number of years. More recently CeRAM is one of the development projects at the ARM spin-off Cerfe Labs. Some of the newly disclosed results should help move the technology forward at a greater pace.
One of highlights of the newly released pieces of supplementary data are some previously undisclosed and remarkable AFM (atomic force microscope) scans of carbon doped NiO CeRAM films. Two examples from many are shown in Figure 1 along with a TEM (tunnelling electron microscope) view of a discrete memory structure.
One of the scans shows three concentric box-shaped regions of an AFM for a large area of a CeRAM memory film (NiO in this example), the outer-most of which is the material in its Born-On low resistance state. The next a darker region is the same material RESET to its high resistance state, using a 1-volt pulse. The third and central region is the same material SET to its low resistance SET state using a 4 Volt pulse. In this type of AFM scan the brightness is a measure of electrical conductivity. The outer and central low resistance regions could be of the same or different electrical conductivity determined by the choice of SET current.
The second scan shows region of the films into which geometric patterns have been written, including the number “3” by applying a RESET pulse to the Born-On film, with the resistance plotted as the height on the vertical axis. The scans are obtained using the tip of the AFM to RESET the material and then measure the electrical resistance.
CeRAM An Overview
For those readers who may not be familiar with CeRAM and its operation, here is a quick and much simplified overview. As the inset in Figure 1 shows the memory device is a simple symmetrical thin film electrode-oxide-metal sandwich with ideally ~30nm active material, a transitional metal oxide doped with 1 to 2% carbon. These are doping levels much higher than those used for the doping of single-crystal semiconductors like silicon with which most people are familiar.
That higher level of doping gives access to what is described as a new type of electronics and bulk switching, which is based on the energy band gaps created by the electrostatic repulsion between electrons. The band gaps are related to the energy required to overcome those electron interactions. These gaps differ from conventional silicon where electrons are not considered to interact with each other, interaction is only with the crystal matrix.
Before the discovery of the CeRAM memory effect, the work of Sir Neville Mott and others provided an explanation of why materials like, for example, nickel oxide (NiO), which by conventional band theory analysis should be electrical conductors, are in fact insulators.
That earlier work looked at the potential energy associated with the Coulombic repulsion between electrons, which results in what need to be called Mott-gaps to distinguish them from the crystalline semiconductor gaps. It established that a boundary existed, based on the count of electrons around the nucleus which separated electrical insulators from conductors.
Prof Carlos Paz de Araujo, Chris Williams, and Jolanta Celinska were first to discover that carbon doping of NiO, and now other TMOs, can be used in a memory device structure as a means to control the backwards and forwards movement across an insulator-resistance boundary, offering the possibility of a new type of non-volatile memory device. They were able by electrical means to selectively screen or un-screen the effects of repulsion and respectively close or bring the energy gaps created by carbon doping into play.
New Materials and Characteristics
A typical example of CeRAM I-V characteristics is shown in Figure 2. These are for the overall voltage and current characteristics of a single 1T1R memory cell, that is for the CeRAM and the series transistor, not just the CeRAM alone. The transistor in saturation is used to provide the compliance current during the SET (from the high-resistance state, HRS to the low-resistance state, LRS) resistance transition.
These characteristics also show how it is possible to use the SET current to control the RESET current and voltage. The flat region of the characteristics, to the upper right of the figure, is where the CeRAM has switched to its LRS and the current is controlled by the saturation current of the series transistor. Some of the implications of this form of presentation will be covered in the discussion section of this post.
The devices are fabricated in what is described as the Born-On low-resistance state with metal-like resistance characteristics. The Born-On state is normally at the lower end of the range of the resistance values to which the cell can be programmed, with other higher values determined by the value of the SET current and the electron injection.
The Born-On state of carbon doped transitional metal oxide (TMO) based CeRAMs is noteworthy because it is one of the features which distinguishes CeRAMs from other competing oxide-base memory devices. Other distinguishing features are:
- The memory devices do not require in-situ Forming
- They are capable of unidirectional operation for both RESET and SET in either the first or third I-V quadrants and bulk switching.
The RESET switching current and current density are key joint requirements for the transition to the HRS formally described as a semi-insulating state.
While most of the earlier work on CeRAMs was focussed on carbon doped nickel oxide (NiO), there were some claims of other TMOs.
To reinforce those claims Figure 3 (a) provides the actual I-V characteristics of the new carbon doped CeRAM materials HfO2 and YTiO3, which along with NiO illustrate the universal nature of the carbon doped memory effect. With now a very low voltage material, bismuth oxide, a post-transition metal oxide can be added to the list of carbon doped CeRAM materials.
In Figure 3(b) some new insight has also been provided which shows how the carbon content controls the switching characteristics. Although the curve parameters of the doping level are not provided, the norm would be 1 or 2%. I understand even at doping levels above 10% that the CeRAM memory effect is still observed, although with a higher level of leakage current.
The results from detailed analysis of small CeRAM memory arrays are also provided as part of the newly disclosed data.
Before looking at more detail, Figure 4 provides a quick simplified overview of the design space for CeRAMs which has so far been explored. It plots peak current density at RESET as a function of device area, where the other variables such as doping levels, thickness, device geometry, operating currents, and processing variables can position a particular device anywhere in the two CeRAM green and orange areas.
The green area is where the CeRAM switching effect is not affected by any unwanted process related variables.
The orange area is where fully working CeRAMs are produced, with all the expected memory characteristics but burdened with extra current. For those devices there appears to be a possibility of two parallel paths for the current, one along an interface surface as shown, the other along grain boundaries in the core of the device, where the presence of oxygen vacancies and structural defects would be expected. The latter would create a pseudo bulk-like switching effect.
One such path along sidewall as illustrated in the inset of Figure 4. Those current paths resulting from different doping levels, oxygen vacancies, or even device geometry, are especially prevalent for the smallest devices.
Part of the reason for this is that most of the CeRAMs produced to date in research laboratories and universities have lacked precision in the processing that would be available in a modern semiconductor fabrication facility.
The uppermost red area in Figure 4 at higher current densities, of the order or greater than 107 Amps/sq-cm, is for ReRAMs, where significant electromigration and even electrostatic effects can move and modify the structure to create and remove conducting filaments or conducting surfaces.
A key part of the new disclosures comes from photoconductivity measurements on carbon doped NiO and clearly show the band gap reduction from the values of about 3.9eV for NiO to 0.9eV for the doped CeRAM material.
In the later “Devil’s Advocate” section of this post I will examine in more detail some of the results and explore some of the possible implications.
Carbon Doping of TMOs.
The result of carbon doping is to change a normally insulating NiO material into a low resistance material with metal-like conducting state which in a device structure can be switched between the two resistance states.
Figure 5 illustrates the manner in which it is claimed the carbon fits in to the NiO structure, replacing an oxygen atom to create what is the key structural element or NiCO molecule which underwrites the operation of the CeRAM.
The cell cross-section on the left side of the diagram shows the carbon-doped NiO key structural element in yellow, and the similar un-doped NiO in white.
Carbon doping at say 2% would see many of those doped key structural elements in a three-dimensional matrix of undoped NiO, with sufficient visibility one-to-another to allow statistically a network of multiple three-dimensional conducting paths of the Born-On state through the matrix. When, as described earlier, the screening electrons are removed the result is a semi-insulating state.
During fabrication this key structural element is created by combination of bonding and electron orbit changes and a redox process between two nickel atoms.
The CeRAM I-V Characteristics: A Different View
A quick and simplified more detailed view of the electrical and switching I-V characteristics for CeRAM (left), and what would be its associated matrix isolation transistor (right), are shown at the top of Figure 6, which provides a view of the voltages and currents for each device in the memory stack, as the red and dark blue curves. The charts below these two form a series that shows the interactions between the CeRAM element and the transistor , with the transistor acting as the load for the CeRAM.
My form of I-V presentation differs from those in the APL paper and Figure 2 where the authors treated the CeRAM and transistor as a single two terminal component, a form of presentation which tends to conceal more than it reveals in the form of what appears to be a hidden characteristic.
For an as-fabricated CeRAM there will be some value of current and voltage (Vreset and Ionmax) below which RESET switching will not occur. The Born-On state is usually the lowest-resistance of the possible states.
Frame 6(a) in the switching sequence is with the memory in either its Born-On or low resistance metallic state and would be one of a series of similar frames as the applied voltage is increased until, at frame 6(b), RESET occurs, when the CeRAM is at Vreset and Ionmax (gold dot). RESET results in a rapid transition to a stable high resistance state, marked with a green dot.
With the CeRAM now in its HRS as the applied voltage is further increased, frame 6 (c), until at frame 6(d) where the voltage seen by the CeRAM reaches the SET voltage (Vset), at which point (yellow dot) a rapid HRS to LRS transition occurs. It is clear when SET has occurred there is not a solution as an intersection point for the blue and red curves of the two devices electrically in series. The only option would appear to be oscillation as indicated in (e).
In the inset box the gold curve in 6(f) provides a reason for the absence of oscillations and an answer to a question which must be raised with respect to the form of the presentation shown in the right side of Figure 2 where RESET and SET currents are apparently equal. It answers the question: Why when the device has switched, and the compliance current is the same as the value required for the LRS to HRS transition, does the circuit not go into oscillation?
This is accounted for by what is described by the proponents of CeRAM as a “dwell time”. This could be a delay time which after the SET voltage is applied and before the switching transition to a stable LRS is completed. With the implication that if the SET pulse is removed before the delay time has elapsed then RESET will not occur. The gold curve in Figure 6(f) is the suggested I-V characteristics for this transient or delay state.
An alternate possible answer, especially for large area devices could be that the self-capacitance results in a large switching transient current (i= Cdv/dt) which SETs the CeRAM to a lower resistance state, the gold curve in (f) which would be a fixed characteristic. This would be fine for single cycle switching, but might cause a problem for life cycle testing.
It is also possible that the “dwell state” is conduction by an alternate parallel path, in which case it would be available for conduction until the current is removed. A parallel path model for CeRAM switching and NV would involve a different conduction path, possibly related to tenuous contacts made and broken, spread over the area of the electrode interfaces. This aspect of the CeRAM will be discussed in the “Devil’s Advocate” section of this post.
In normal operation, and to avoid any oscillation-like problems, the SET current would be selected to be lower than Vreset and Imaxon, so from the practical viewpoint the question of oscillations, while of interest, is academic.
The CeRAM is fabricated in a Born-On state. Because it is possible to SET the device to a range of resistance states, the Born-On state is normally at the lower end of the range of its possible programmable resistance values, with other values determined by the value of the SET current and the electron injection. The indications are irrespective of the SET current: RESET always returns the device to a fixed state as indicated in Figure 2.
A Little More Detail
It is claimed that fabrication, carbon doping, and annealing complete all and any of the structural changes associated with the CeRAM. From then forward all changes are claimed to be the result of electron injection and extraction and the removal and replacement of screening electrons.
The ability to transition between what appear to be two very stable resistance states, or to be able to cross the conduction-insulator boundary with very little effort, energy or power, would suggest some positive feedback mechanism must be at work, which once triggered completes the rapid transitions.
The following figures provide a simplified graphical explanation of the stages in that feedback mechanism and the carrier changes occurring between the electrodes which underwrites the observed two terminal electrical characteristics for a RESET-SET-RESET memory cycle described earlier.
The upper diagrams in this sequence show the voltage and, from slope, the electric field across the device. The lower figures describe the way in which the carrier types involved in the conduction process change as the device switches.
Initially (a) the field is constant and, as the voltage is increased, it is claimed the current flow involves both electrons and holes.
This continues until, at Vreset (b), an imbalance occurs close to the anode which causes most of the voltage to be applied to that region. At some critical value of applied voltage and current (Vreset and Imaxon) the rate of electron removal creates an electron-hole imbalance close to the anode.
The region rapidly expands to embrace the whole space between the electrodes (c) creating a domain of hole-rich semi-insulating material which rapidly propagates to fill the complete space between the electrodes. The result is the semi-insulating state, now with the same voltage applied and little current flowing. which RESETS the device to its HRS.
To SET the device to its LRS, the voltage is further increased to the SET voltage, Vset (d), where sufficient electron injection close to the cathode introduces screening and creates a domain of screened conducting material.
This causes an increase of voltage across the remaining high resistance material. Driven by the increased potential the conducting region rapidly expands to complete the transition to re-establish the low resistance conducting state (e).
Keep in mind that these band gaps (Mott-gaps) and bands are the sum of the electrostatic forces at the single atom level where the local density of electrons and screening effects determine if the gap is closed or open, i.e., screened or not screened for the two resistance states of the memory.
While the electric field description of the RESET and SET operations is a useful aid to understanding, the rate at which the process of hole domination occurs for RESET is claimed to be enhanced by what is described as an electronic phase transition, resulting in a high resistance M-I-M device, based on p type conduction.
A measure of the stability of the two resistance states on either side of the boundary is provided with disclosures of operation at temperatures of 400°C and as low as 1.5°K for symmetrical first and third quadrant operation. In memory device form, the two CeRAM resistance states are very stable, with new experimental evidence in the APL paper of data retention at 400° C for over an hour and retention of both states almost unaltered for 24 hours at 200°C.
Resistance as a function of temperature for the conducting state indicates metal-like characteristics. The calculated temperature coefficient of resistance for the conducting state is 2.27 x 10-3 Ohms/degree K.
The simple model that best fits the observations is one where in the Born-On low resistance state, all of the possible screening electrons are in place as a result of the fabrication process. The action of RESET always removes all of the screening electrons, irrespective of the resistance to which the device has been previously SET. If so, the RESET state resistance would be constant for a given device structure, which is close to what is observed, for the HRS, in the lower of the curves in Figure 2. This means that the result of variations in SET current is to replace some fraction of the screening electrons up to the maximum that were present in the Born-On state.
The concept that an interface effect would trigger switching might raise the expectation that film thickness and switching voltages and currents would not be closely related. In that respect the key piece of data will be the plot of LRS and HRS at the read voltage as a function of thickness for devices of the same area. When available, that data might allow the possibility of interface switching to be eliminated or confirmed. I’ll provide more discussion of that in the “Devil’s Advocate” section.
Given that model, are the different values of SET resistance the result of the same levels of screening around each nucleus, or the result of statistical variations in screening throughout the material volume? In effect, some conduction paths are blocked while others remain open.
An interesting, and perhaps for some a disarming feature of the new electronics and Coulomb repulsion effects, is the activation energy of resistance as a function of temperature for the HRS RESET state. It is not, as might be anticipated for a material with a band gap of between 0.7 and 0.9 eV, obtained from photoconductivity measurement; it is of the order 0.23eV, calculated in the conventional way as [R = Ro (e^E/kT)] from the elevated temperature data.
The difference between Born-On screening and screening during SET is key to understanding the operation of the CeRAM. When current is flowing the concept of screening as a dynamic effect is easily accepted. When the current is removed and in the Born-On state, the interesting question is why and how is the non-volatile screening state maintained?
CeRAM The Devil’s Advocate
In this section I will address some the concerns of those who hold the view that mechanisms other than those associated with correlated electrons could explain CeRAM switching. I will explore the possibility that the two non-volatile resistance states of a CeRAM might be related to a secondary mechanism which operates electrically in parallel or in series with the carbon doped TMO material. For this there are three pieces of experimental evidence from the recent CeRAM disclosures by Symetrix which help to serve as a rebuttal.
How well do other possible explanations for the characteristics of the CeRAM, such as electromigration, filaments, surface barriers or even surface catalysis match with the observed CeRAM characteristics? Or is there a silver bullet observation or CeRAM characteristic which eliminates all of those possibilities?
While a simple metal-TMO-metal sandwich describes the CeRAM structure, what emerges from a closer look is a more complex picture of crystallite grain boundaries and complex oxide-electrode interfaces. In a simplified form, these complexities are highlighted in the illustration of Figure 8.
It is a picture which raises the possibility that parallel conduction and switching paths could exist. These paths would be along or at the ends of grain boundaries, resulting in pseudo bulk switching characteristics. Added to that is the possibility of surface effects from the complexity of the electrode-TMO interface. These surface effects would develop in the presence of powerful catalysts such as Pt, Ir or IrO electrodes, where there is likely to be an abundant supply of poorly bonded oxygen, nickel, carbon, and oxygen vacancies, and where the perfection of the substitutional carbon doping in the NiO crystallites, essential to the description of CeRAM operation, is lost.
A further complication is, up until now most of the active oxide film has been deposited using spin-on techniques which means the upper surface Electrode-NiO interface is likely to have some form of roughness compared with the one at lower electrode. The form of the upper electrode interface shown in Figure 8 is one used for illustrative purposes as a means of highlighting the difference between it and the lower electrode.
A rough surface structure is likely to result in local regions of high electric field or current density and cannot be ignored in any attempt at modelling must take this into account.
ReRAM Switching Mechanisms
The ability to RESET and SET CeRAMs with unidirectional voltage and current in the first or third I-V quadrant would appear to rule out most of the conventional ReRAM type mechanisms which require bi-directional current and voltage.
What is the possibility that the two NV resistance states are based on a ReRAM-like switching effect in some parallel or even serial path, with electromigration and back diffusion as a possible RESET-SET mechanism?
The recently published work can be used to help clarify an understanding of the effects of the sidewall conduction, and comes in the form of Figure 9(a) which is a plot of current density as a function of device diameter, shown as the CD in the figures.
In the right-hand Figure 9(b) I have overlaid on the original two new curves. The red curve shows what would be expected for a family of CeRAMs consisting of two parts, a 1nm wide sidewall electrically in parallel with the body of the active material, coloured orange and grey respectively in the inset of Figure 9(b).
This curve is based on my calculated characteristics for CeRAM devices with a sidewall current density of 9.5 MA/sq-cm and 0.88MA/sq-cm for the remaining body of each device. The red curve family of devices matches exactly the average of the original current density plots. The choice of a dimension for the sidewall width would change the two calculated current densities. From my calculated red curve a side wall current of 90nA/nm can also be extracted.
The horizontal green curve on Figure 9(b) shows what would be the expected characteristics for CeRAMs unencumbered by unwanted sidewall effects, i.e., perfect devices.
Any attempt to characterise this side wall current as the result of a low resistance or leakage path from oxygen vacancies or the like is frustrated because that leakage path is not present when the device has switched to its HRS. This would mean that any existing sidewall path must also switch to a high resistance state when the body of the device switches, suggesting it is more likely to be over-doped active material combined with some shape effect.
The experimental evidence, device-to-device does not suggest that the sidewalls are multi-filament in nature; if it were then any filaments would have to be evenly spaced as the length of the sidewall increases. Since the side wall current (nA/nm) remains constant with increasing radius the best fit would probably be an annulus shaped structure.
If the sidewall conduction is annulus shaped and is the result of a different level of carbon doping, then we must accept that any compositional inhomogeneity, in relation to carbon doping in the body of the device, could result in filamentary conduction, to be added to the list of fabrication defect effects.
Symetrix provided me some of their unpublished measurements in a private communication. These measurements, taken from Symetrix’ plot of current/peripheral length (nA/nm) as a function of device diameter, show that a sidewall current of 100 nA/nm is obtained for the same devices with diameters from 46nm to 93nm.
From that piece of data, and based on the assumption that the width of the sidewall is of the order a nanometer, the sidewall current density would be of the order of 107 Amps/sq-cm. While those current densities might result in resistance changing ReRAM-like electromigration effects, what is the unidirectional current related mechanism that is able to reverse it?
For those searching for possible grasping-for-straws explanations, history might provide a clue. In the past unidirectional current related flow break-and-repair was observed with nichrome resistors used in PROMs. This effect was seen as attempts were made to geometrically scale those devices. Failures would be observed with the fused nichrome resistors returning from the open circuit HRS programmed state to the low resistance conducting state.
At the time, the behaviour of oxygen vacancy conduction and ReRAM mechanisms was less well understood that it is today. It is not clear if the failure mechanism was the regrowth of a nichrome metal link or a parallel path in the oxide. In terms of a memory effect it was a case of short write time, and for the failures in the field a long erase time. Both effects were observed with unidirectional current and the return to the LRS at a very low applied voltage.
It is worth remembering that the side wall current paths are only seen in fully working CeRAM un-passivated devices fabricated in the “Fabrication Related Defects” area (orange) of Figure 4
The fact that the low resistance side wall current paths are not apparent when the device is in its HRS must mean those paths have switched or been removed for a CeRAM in its high resistance state. Their reappearance in the SET state is an indication that a unidirectional reversible switching is possible for whatever causes the sidewall current. A more likely explanation is the reversible switching of the sidewall is a result of just carbon over-doping at the sidewall interface, possibly even from zone refine-like rejected carbon, or a geometric shape effect.
If the sidewall has different switching characteristics, i.e., lower SET voltage due to higher doping levels, then that region would be expected to SET before the core of the device. The resulting reduction in applied voltage across the rest of the device would prevent the core from switching. The fact that this does not happen needs to be reconciled with different switching characteristics for doping levels as shown in Figure 3(b). Further investigation might help the case for or against bulk switching.
In the other direction, lower levels of carbon doping, where the CeRAM is a network of multiple conduction paths linking the structural elements (as illustrated in Figure 5), do lead to considerations of multiple nano-filament conduction.
Statistically, at some lower level of doping, the probability of complete conducting paths must drop to one, and then to none. One single path of doped material would shift the CeRAM from a bulk switching device to inverse filament switching. Figure 3(b) confirms that lower levels of carbon doping would possibly lead to fewer conducting paths and a high resistance material. A single path would result in a device switchable between two high resistance states.
In the same manner as the sidewall switches, a CeRAM filament model could also be the result of composition variations across the bulk. This is not fundamental, but would be a fabrication defect.
Catalysis and CeRAM Interface Switching
Next on the list are interface effects. The received wisdom is that RESET is initiated at the NiO- electrode interface. What must be eliminated is the possibility that while carbon doping produces a low resistance NiO, the Born-On LRS of the oxide is either permanent or capable of dynamic volatile switching and the two memory states are related to changes at the electrode interfaces.
Oxide metal interfaces are not well understood. One consideration must be the possibility that at the nano-level, as a result of carbon doping, there are two parallel paths distributed across the whole of the interface surface. For example, one provided by conduction along grain boundaries and a second through the oxide. The roughness of the spin on doped-NiO might be considered a candidate for such an effect.
One of these is modified by electromigration to create the high resistance state, then repaired during SET, when in a parallel surface path tunnelling through the second high resistance contact areas creates the conditions for repair. Such a mechanism with two conduction paths in play might account for the “dwell state” mentioned in the earlier circuits section of this article.
Electromigration and back diffusion might be one mechanism. Another might be electromigration and some form of zone refining-like effect which rejects say the carbon. This would involve the lateral movement of a conducting species (nickel or carbon) into the crystal interface, then a zone refining-like mechanism to push it back into the conducting path.
When any sidewall current is removed, the current density for the core of the device is of the order 104 – 105 Amps/sq-cm, (see Figure 4 and the green curve of Figure 9(b)). This would mean that any interface switching effect requiring electromigration would have current below the values where electromigration would be expected to be possible in a short time period, unless the current is highly localised at contact points across the surface.
Figure 8 illustrates that, at the electrode interfaces, in the presence of powerful catalysts such as Pt, Ir or IrO, there is likely to be an abundant supply of poorly bonded oxygen, nickel, carbon, or oxygen vacancies. That combination raises the possibility of catalysis and might suggest that a low temperature oxidation reduction process could be occurring at the electrode interfaces. It is worth remembering that during fabrication the key structural element is created by a combination of bonding and electron orbit changes and a redox process between two nickel atoms.
Pt acts as a catalyst because it is able to provide free oxygen ions to any process with which it is involved. A suggested mechanism would be low temperature oxidation and reduction at the electrode surface to create the two memory states. Another possibility would be that catalysis and electromigration are responsible for the two memory states. A third would be that the equilibrium of the redox from carbon doping is disturbed.
Strong Evidence of Bulk Switching
One piece of experimental evidence that was included in the research paper, evidence which tends to eliminate switching at a single interface, is shown in Figure 10 and comes close to the silver bullet proof for bulk switching. It involves RESET (red) in the first I-V quadrant and SET (blue) in the third quadrant, shown in 10(c), or SET (blue) in the first I-V quadrant then a RESET (red) in the third I-V quadrant, as shown in 10(d).
The value of the experimental evidence of Figure 10 can be best understood by considering an experiment starting with the device in its Born-On state and then RESET, with only one interface switching. Now, reverse the polarity to SET the device. While the supposed high resistance surface would SET, the opposite surface would RESET leaving the device in its high resistance state.
This would strongly suggest any interface switching mechanisms would need to RESET or SET both surfaces for each switching operation, which might tend to eliminate a mechanism that employs a direct and very localised opening and closing contacts at the electrode surface.
Other Switching Related Questions
There are a number of other CeRAM interface switching mechanism related points of interest that arise from another part of some of the recently released data. These come in the form of the results of an experiment whose primary purpose was to establish the difference between CeRAMs and ReRAMs, and doped and undoped NiO.
That was to show the ReRAM needs a Forming voltage that is higher than its lower operating voltage, while for the CeRAM the switching voltages are the same for the first and all subsequent switching events.
For this experiment, and as shown in Figure 11 (a), the initial structure was a sandwich consisting of a thin film of un-doped NiO between carbon doped films of NiO, with the electrically conducting doped NiO in its Born-On low resistance state initially acting as electrodes for the ReRAM structure. The device
was Formed and switched as a ReRAM to create a conducting filament in the undoped NiO between the two doped NiO films.
Once the ReRAM filament was Formed in the undoped NiO, displaying the normal high Forming voltage, it was reported that the CeRAM parts of the structure operated in the normal fashion with the conducting filament of the ReRAM apparently acting as an electrode, the anode for one of the series CeRAMs and cathode for the other.
The first point of interest, away from the main purpose of the experiment, is the normal operation of the CeRAMs with the Formed metallic filament consisting of Ni or oxygen vacancies, or a mixture of the two, and possibly some carbon, acting as the anode electrode for one of the CeRAM structures. This casts doubt on the need of high work function material like Pt, Ir or IrO as an essential CeRAM requirement and would seem to eliminate the possibility of catalysis-based switching mechanism.
A second point of interest from this experiment relates to RESET, where there is a need of a minimum critical current density to initiate CeRAM switching close to the anode and then propagate the switched domains. Therefore, for the two CeRAM devices in series, only one end of the filament acting as the anode can reach the required current density. The current at the other anode is spread across the larger surface area of the Pt electrode.
Figure 11 (b) illustrates one possible manner in which switching might occur with only one anode able to reach the required current density. If so, then only one of the series CeRAM devices is capable of operating while the other must surely remain in its conducting state. Or, if the presence of a high work function electrode is essential, then the alternative explanation is that the device with the larger area anode is first to switch and the CeRAM in series with the filament anode fails to switch.
Figure 11(c) highlights another point of interest regarding the requirement for a critical current density and electric field is required to switch and propagate the switched domain then only a limited dome region of the doped NiO will switch before the required conditions at the switching interface are lost. While Figure 11 (d) would be the suggested conditions when the presence of high work function Pt, Ir or IrO is essential. If the CeRAMs operate normally then it makes the case for a surface triggered electronic phase transition as the basis of CeRAM switching. I will leave as an open question the degree to which triggering of an electronic phase transition, at a small electrode surface results in a filament of switched material, or does the whole volume of material between electrodes of different areas switch?
Figure 11(d) illustrates switching when presence of a high work function electrode material in contact with the electrode is essential.
Even allowing the imagination to run riot, it is difficult to make a case for a mechanism other that bulk switching to account for the observed operation of the CeRAM. Applying Occam’s razor to the different possible alternative mechanisms, both those imagined or those formally proposed, is of little help as all are equally complex.
Where Does CeRAM Go from Here?
The newly disclosed results in the APL paper include a very detailed theoretical analysis which appears to be valid, although it will have to be tested elsewhere in higher halls of learning to ensure it is an accurate description of the experimental and two terminal device observations.
From a practical point of view, the new evidence would appear to suggest the CeRAM meets most of the requirement of an ideal memory. Why then has it been so slow to move into the mainstream?
Here are a couple of possible reasons: Most of the work has been carried out with spin on films. There may be a reluctance to use spin on for an active material, although nowadays spin-on can produce films in the single digit nanometer thickness range with interference wavelength precision, so reproducibility control should be too much of a discouragement.
Could it be electrodes? The electrode-TMO interface is a very important contributor to the successful operation of the CeRAM. Up until now most of the CeRAM devices have required the use of high work function materials such as platinum or iridium as the electrodes, with iridium oxide as a candidate material. Perhaps there are other factors which have discouraged third parties from entering the fray. The comment section below is open for those who might have a view.
What CeRAM needs is for one of the large memory companies with the entrepreneurial spirit to be brave enough to provide the means of fabrication and circuit design for large memory arrays to give CeRAM the push it appears to need.
I would like to thank the staff at Symetrix and Cerfe Labs for their kindness and patience as I have reduced the complex detail of their device and new disclosures to a few words, plus as always, the tolerance of the purists for my oversimplification of theoretical detail. Mea culpa.
 Universal non-polar switching in carbon-doped transition metal oxides (TMOs) and post TMOs. APL Materials 10, 040904 (2022); DOI: 10.1063/5.0073513
 CeRAM: Extreme Temperature (>200°C), Radiation Hard ( >1 Mrad), Dense (sub-50 nm CD), Fast (2 ns write pulses), Non-Volatile Memory Technology by Saurabh Suryavanshi, Cerfe Labs. Session 3, Poster P1, International Memory Workshop, 2022