In this post contributor Ron Neale looks deeper into a paper delivered by CEA-Leti at December’s 2019 IEDM conference, evaluating its fundamental thesis that an OTS selector is suitable for high-density memory arrays. Another interesting aspect of this same paper was the subject of an earlier post.
One eye catcher at IEDM 2019 was a paper from a team in France at CEA-Leti, Minatec, Grenoble, IMEP LAHC CNRS and INL CNRS, INSA Lyon, by D. Alfaro Robayo et al titled: Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration. I discussed another aspect of this paper in my previous post. This paper confirmed and highlighted the importance of the chalcogenide based thin-film selector as an essential memory cell component for the future, not just for phase change memory (PCM), already established by Intel with 3D XPoint and Optane, but also for oxide-based storage or persistent class memory arrays. This selector type is important because of its ability to provide matrix isolation for memory devices requiring either unidirectional or bi-directional current flow during the write operation.
The goal of this team effort was to link the measured statistical variability and reliability at the device level to the requirements for use in very large 1Gbit oxide based memory arrays. From the details provided in their paper the effort must be marked as successful and points to a positive future for very large oxide-based memory arrays constructed using sub-20nm lithography.
At the device level the vehicle for this investigation was a memory cell stack (illustrated above) which combined the team’s very low leakage, best-in-class, Nitrogen doped Germanium Selenium, Antimony (GSSN) selector with a Hafnium Oxide resistive memory device. (See the table in this post.)
Constructed on a 150nm CMOS process the memory cell stack consisted, from the silicon upwards, films of: TiN, Carbon, GSSN, Carbon, TiN, HfO and Ti/TiN. The GSSN thickness ranged from 15nm to 25nm while the HfO had a thickness of 10nm. The selector thickness range was used to optimally control leakage or threshold voltage.
The three key features investigated in this work were:
- The current margin at Vread (Ion/Ioff)
- The selectivity (Ion/Ileak)
- The voltage margin (ΔVth= Vth1 -Vth2)
Those variables are highlighted with a gold star in the following chart, which plots log current as a function of voltage for Forming and for the High Resistance and Low Resistance states for the 15nm 1S1R selector/memory combination shown at the right. Vth1 and Vth2 are the cell switching voltages, with the OxRAM in its high resistance state (HRS, blue) and low resistance states (LRS, red) respectively. The third line (gold) represents Forming, which was discussed in depth in another of my posts. (The inset in the green box will be explained later in this post.)
The Forming voltage for this cell is 5V while the operating range for Vth1 and memory Reset is about ±3Volts.
Not unexpectedly the higher series resistance of the memory’s HRS will make the threshold voltage of that combination higher.
The combined leakage current of all the series/parallel devices in the sneak paths of a memory array will compromise the ability to read the On state of a device, making (Ion/Ileak) a very important parameter. The leakage current before Forming tests the current measuring limitations of the test equipment, at read voltages close to Vread/2.
Any and all of those key parameters will each be part of a statistical distribution which itself will change over time and operating cycles. Combining those measured variations with simulations, the team provided, for the first time, a realistic crystal ball view of what might now be possible for memory cells combining an HfO memory and a GSSN-based chalcogenide selector.
Of note is the use of a thin film of carbon as the electrode or interface for the GSSN device; the authors report this is needed as a barrier to prevent the diffusion of TiN into the GSSN selector material. It is interesting because Intel, for their Optane memory, employ carbon, not for the selector, but as the interface electrode for their GST (GeSbTe) memory device.
Which raises an important question: If for Intel a diffusion barrier is required for the GST of the memory element, why not for the very similar arsenic-doped GST of the selector? It is possible that for the Intel device the carbon is used to allow for what might be described as RESET overdrive to ensure that all of the memory material is returned to its amorphous state. It is especially important to clear the corners of crystallized material for a device with a square cross section in the plane normal to the direction current flow. Carbon would also serve to avoid a fixed crystal-molten GST interface, which, because of the different directions of movement from electromigration and electrostatic effects, can cause a concentration build-up of one element at that interface. At the same time this would also avoid any chemical reaction or diffusion because of high temperatures during processing.
For GSSN threshold switching, the choice for this team was a model based on field-induced nucleation theory. Their model assumes that threshold switching starts at the cathode with the nucleation and growth of a filament consisting of a series of electrically conducting metastable domains to bridge the inter-electrode gap. This assumption moves away from the idea that threshold switching is based on a bulk phenomenon, and that’s a significant step. This switching model is illustrated in part (a) of the figure below, with the initiating filament having an end radius 3nm, that grows vertically to bridge the inter-electrode gap.
Part b) of this figure illustrates one possibility of events after the conducting filament has bridged the inter-electrode gap. In this diagram the initiating filament expands to deal with the post-switching conducting state current, versus the alternative of the dissipation of the conducting state within a fixed radius filament. I raised this question with the paper’s lead author Dr. Diego Alfaro Robayo, who at the time of the papers publication was a PhD candidate at CEA-Leti. His email reply:
“At this level, we do not need to simulate ON state conduction. Consequently filament expansion after switching was not considered in our model, and could be something to have in mind for further studies requiring ON and OFF state conduction description.”
Forming
Alfaro Robayo’s reply was of particular interest to me, following my recent foray into the unknowns of Forming. For a chalcogenide-oxide memory cell, both the memory and selector require Forming, which occurs at the same time during the same switching cycle (the gold line in this post’s second graphic). The threshold voltage for Forming both devices is about 5V while the operating range for Vth1 and memory reset is about ±3Volts.
The cell Forming voltage varies with thickness with a coefficient of ~1V/5nm, while after Forming it is reduced to 250mV/5nm. For a GSSN thickness range from 5nm to 25nm this translates to a Forming voltages ranging from 4V to 8.5V respectively.
In the memory array the programming current source must have adequate voltage for Forming as well as for Vth1. Also (Vforming/2) must not exceed Vth2, or even Vth1, in order to prevent spurious switching. The inset box in this post’s second graphic, replicated below, illustrates (the grey curve) why the need for the statistical analysis of this work at the device level is such an important consideration for any future memory array predictions: as the dispersion of the more variable High Resistance state (HRS – blue line) can result in an overlap of the HRS and LRS for some cells, causing HRS cells to be read as LRS (red line). The outliers in the grey curve of the cell are mostly caused by the HfO memory device.
On that subject I raised the following question with D. Alfaro Robayo: “In your proposed memory array, how do you deal with Forming when both devices in the cell are in the as-fabricated state? For your devices with thickness of 15 to 25nm the voltage would vary from 5 to 8 volts respectively. I assume there is sufficient voltage from the (100μA) programming source/drivers to provide the required voltage. Is that correct?” He commented:
“Definitely, our forming voltages are very elevated and hardly compatible with advanced CMOS generations. In our case, we can reach these voltages as we work on a relaxed technology node. For future implementation, large transistors or amplification techniques (cascade…) would have to be used to reach these voltages. This may not be critical as only one transistor is required per row (or column) in crossbar configurations (precise dimensions and analysis would have to be performed for a given technology node), thus, these large transistors may be integrated in the logic under the crossbar array without area penalty. “
Conclusion
The bottom line, from all the careful measurement, statistical analysis and simulation of 1S1R (GSSN-HfO) memory cells, is an impressive list of performance characteristics and the associated reliability limitations shown in the following table:
|
Device Feature |
This Work |
Impacted By |
|
Selectivity |
10^6 |
GSSN Leakage |
|
Endurance |
6 x 10^6 |
HfO Endurance |
|
Read Cycles |
10^8 |
GSSN Endurance |
|
Current Margin |
10^3 |
Iprog/Ioff |
|
Read Voltage Margin ΔVth |
1Volt |
GSSN and HfO Variability |
From that list the team identified voltage read margin variability as the key to success with this type of 1S1R memory, where the statistical variations in the characteristics of the HfO OxRAM can sometimes cause the outliers of Vth1 and Vth2 of the cell to overlap, compromising the read operation with a failure, as illustrated in the most recent graphic. Great care is required in the selection of the cell’s Vread voltage.
An important end result from the combination of the very low leakage current and narrow filament is that with lithographic shrinking the selectivity should stay almost constant, or even marginally improve.
While offering positive projections for GSSN selectors on memory array sizes up to 1Gb employing 25nm thickness at the 14nm lithographic node for GSSN, the team acknowledged two important limiting factors: 1) voltage drops in array conductors and 2) the ratio of memory array size to memory area peripheral owing to the high voltages required for Forming.
While the “S” type negative resistance I-V characteristic of threshold switching has always been a strong indication that this type of switching is filamentary in nature, an important aspect of the CEA-Leti paper’s work is the fact that the team appear to offer strong support for that interpretation, against the alternative of bulk switching. The important open question, when with scaling the dimensions of the stack structure itself reaches 6nm, is whether switching becomes a bulk phenomenon or a destructive breakdown.
I raised with D. Alfaro Robayo a final question: “What are the next steps with respect to the work reported: will it be a product, licensing?” His reply:
– New materials to improve device performances
– Device patterned with smaller dimensions to address scalability and analyse filamentary / bulk behaviour
– New circuits, like crossbar arrays with sense amplifier to be closer to a real product
References.
[1] Reliability and Variability of 1S1R OxRAM-OTS for High Density Crossbar Integration, D. Alfaro Robayo, et al, Proceedings of IEDM 2019.
[2] Extending the Write/Erase Lifetime of Phase Change Memory: Part 1 & Part 2 – A More Complete View of Element Separation, by Ron Neale , The Memory Guy
[3] The Known Unknown series, by Ron Neale, The Memory Guy
