Did Samsung Just Endorse YMTC’s Xtacking?

Closeup of Samsung graphic, showing illustration of wafer-bonded NANDDuring his December 15 IEDM keynote speech, Samsung Electronics Chairman Kinam Kim really surprised me.  He spoke favorably of the approach that YMTC is using to produce 3D NAND flash.

This approach, which YMTC named “Xtacking,” involves the use of two separate wafers to manufacture a 3D NAND chip.  The brief way to describe it is to say that the memory core is made on one wafer using a 3D NAND process, and the peripheral logic is produced on its own wafer using a CMOS logic process.  The two wafers are then bonded together.  It’s a more expensive process, but it got YMTC into the market faster, which was that company’s primary goal.

What Dr. Kim said when presenting this was:

To meet I/O bandwidth requirements, which are expected to double every three years, greater efforts to address thermal budget reduction and thermal budget decoupling are needed. A wafer-bonding process, as an example, that decouples process thermal budget for memory cells and peripheral transistors is one way to accomplish this.

This falls short of an actual endorsement, but it certainly makes me wonder if Samsung may itself plan to use this approach.  It’s not clear from the presentation whether or when this might occur.

The image at the beginning of this post was a small part of a slide showing NAND flash’s history and roadmap from 2014 through 2030.  The whole diagram, courtesy of IEDM, appears below.  (The resolution is low because it was reproduced as one of eight diagrams published on a single page.)

Note that Xtacking appears as early as 2025, while “Cell on Peri(phery)” or COP doesn’t appear until 2020.  COP is Samsung’s name for the CUA (CMOS Under Array) approach that Micron and Intel used to launch their first 3D NAND chips in 2015.  This approach is now used by all flash makers except for Samsung and YMTC.  Samsung also showed “Multi-Stack” appearing at the same time, although that technology was first introduced by Intel and Micron with their 64-layer part in 2017.  In the industry it also goes by the names “String Stacking” and “Decks.”  Until recently, Samsung explained that they did not need to use either of these complex approaches to beat their competitors’ cost structures, so that’s probably why they appear so late in the chart.

With that in mind, it’s a big surprise that Xtacking appears as early as 2025.  Given that this is the first time that I have heard the company even mention the technology, that makes me wonder what Samsung’s plans are for Xtacking.

It’s a positive thing for YMTC, though, to have its approach included in an important presentation by the world’s leading NAND flash producer.

Naturally, I’ll be watching this technology and reporting more in future posts.  For more regular updates on the status of the industry readers are welcome to contact Objective Analysis to see how we can work together to help your company achieve its strategic goals.

 

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