The Memory Guy

Readers who have been following this series will note that The Memory Guy has so far described everything pertaining to emerging memory technologies except for the market outlook.  In this post I will share some key elements of our emerging memory forecast.

Since this is a simple blog post the forecast coverage is brief.  The detailed forecast appears in the report that is the basis of this blog post series: Emerging Memories Poised to Explode.

The first large-scale applications poised to replace today’s standard NOR flash with a new memory technology will be the embedded memories in CMOS logic chips that are processed on advanced process nodes (processes of 28nm and smaller.)  Many CMOS logic chips use NOR flash, especially microcontrollers (MCUs) which are found in a very broad range of applications.  The vast majority of MCUs, though, are uncomplicated and can therefore be economically produced on larger, older process nodes like 90nm and greater.

At tighter processes flashless versions of some MCUs already ship that can download code from an external NOR chip into an internal SRAM cache.  This is a way around the problem that seems to work well in many cases.

Finer process geometries are favored for high-complexity processors like microprocessors (MPUs) and smartphone baseband chips.  These chips often can use an external NOR flash chip to store boot-up and BIOS code (Basic Input-Output Subsystem) relieving any need for on-chip nonvolatile memory like NOR flash or an emerging memory technology.  In smartphones most of the firmware is stored in NAND flash and moved to the DRAM for execution.

This means that for both MCUs and MPUs external NOR competes against internal emerging memory technologies, and this could delay the adoption of emerging memories.

Still, this market seems to be on the brink of a gradual conversion from NOR flash to some emerging memory technology as chips migrate to finer process geometries.  This is very different from the two major stand-alone memory chip markets: DRAM and NAND flash.  DRAM and NAND vendors migrate from one process node to the next much faster, producing the bulk of their product on only two or three process nodes.  When these markets eventually migrate to an emerging memory technology the transition will be much faster.  The figure below provides a rough illustration of how this might play out:

Today it is unclear which emerging technology is likely to win widespread acceptance in embedded applications.  Leading foundries are working on multiple emerging memory types, mostly MRAM and ReRAM, however a lot of attention is being paid to the new hafnium oxide FRAM since it is based on materials that are already used in volume in these foundries.

ReRAM is often viewed as a likely replacement for NAND flash, but this opinion originated when NAND was expected to stop scaling at its 15nm planar node.  After Toshiba introduced the 3D NAND concept in 2006 the use of ReRAM was pushed out for another 3 generations (according to certain early SanDisk predictions) but the advent of string stacking gave NAND’s lifetime a significant extension.  Nobody knows when NAND will finally reach the end of its life, and, in the mean time, something other than ReRAM may become a more appealing alternative.  ReRAM’s appeal is that it uses a two-terminal selector and can thus be packed very densely and can be stacked in multiple layers.

Current thinking shows MRAM replacing DRAM.  There are two reasons for this: First, MRAM is very fast, perhaps equally as fast as DRAM, whereas most other technologies are not.  Second, the selectors for both MRAM and DRAM are three-terminal devices, so the die sizes for MRAM and DRAM are similar for the same process geometry.  Once DRAM reaches its scaling limit then MRAM should be able to travel down the same cost decline curve that DRAM was originally following.

Note that the transitions from NAND to ReRAM and from DRAM to MRAM are far more abrupt than the transition of CMOS logic to an emerging technology, as was mentioned earlier.  The exact timing of these transitions is unknown since researchers  continue to make breakthroughs to extend the  lives of today’s leading technologies.  We have built our forecast around a best guess.

A few of the key assumptions that lay behind our  forecast are:

• Foundry logic is being driven to emerging memories because NOR flash doesn’t exist at process nodes smaller than 15nm, and there is even trouble making NOR flash at larger process geometries that use a FinFET process.
• Stand-alone memory chips should stay with currently entrenched technologies – DRAM and NAND flash – for some time thanks to the challenges posed by the economies of scale.
• Emerging technologies rarely win designs based on technical attributes.  Instead they find their way into applications by providing a cost advantage.  This is nowhere more clear than in today’s smart phones, which use DRAM and NAND flash even though these two technologies are extraordinarily poorly suited to battery power when compared to NOR flash and SRAM.

Based upon these assumptions we have built the petabyte shipments forecast shown on the left.  These forecasts combine embedded memory on CMOS logic chips, stand-alone memory chips, and the Intel/Micron 3D XPoint Memory.  The forecast provides an optimistic scenario, with exabyte shipments (thousands of petabytes) approaching 57 by 2028, a pessimistic scenario with this figure coming in a little over 4 exabytes, and a mid-level number of slightly more than 30 exabytes.  The mid-level scenario would drive 2028 revenues slightly over $6 billion in 2028.

The forecast does not spell out sales by emerging memory type because it is still too early to know which one technology will assume leadership in this market.  It is most likely, however, that only one technology, or at most two, will reach prominence, since most emerging memories have very similar characteristics and all of them can be produced between the metal layers of the base chip.  The economies of scale will allow one technology to develop a significantly better cost structure than any of its competitors, causing the market to gravitate toward a single winning technology.

This post is the sixth and last installment in a series on emerging memory technologies, looking at it from several angles, and predicting how these technologies will change both the chip market and the market for the capital equipment used to produce these chips.  It consists of excerpts from a recently-released report from Objective Analysis and Coughlin Associates: Emerging Memories Poised to Explode.

There are six sections:

1. Why Emerging Memories are Necessary
2. Understanding Bit Selectors
3. The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.
4. Process Equipment Requirements
5. Emerging Memory Companies
6. Forecasting Emerging Memories

The Memory Guy has provided these to help readers understand the emerging memory technologies and markets.  Questions and comments are appreciated.