Something that distinguishes the Emerging Memory report that Tom Coughlin and I recently published is the depth in which we cover in the field. This is not measured in pages, but in the topics that we cover. For example, this blog post, excerpted from the report, covers the changes in tooling that will be necessary to allow a standard CMOS wafer fabrication plant (a “fab”) to produce an emerging memory technology, and the impact that this is likely to have on the market for semiconductor tools.
All of the emerging memory technologies covered in the Memory Guy’s previous post share certain things in common. One of them is that they are built between metal layers, rather than in the silicon CMOS substrate itself (with the possible exception of the hafnium oxide FRAM.)
This means that the tooling required for any of these technologies will bear a strong resemblance to that used by any of the others. For the most part these tools will be used for deposition and etch. The lithography requirements will be satisfied by the tools used to pattern the metal layers.
The process flow in this figure sheds some light on the steps that drive the need for this equipment:
The most important equipment falls into four key categories:
- Physical Vapor Deposition (PVD)
- Photolithography (Patterning)
- Ion Beam and Plasma Etching
- Magnetic Annealing (used for MRAM)
A PVD cluster tool from Tokyo Electron (TEL) appears in the figure below.
The report gives details about tools available from eighteen mainstream tool makers including:
- Applied Materials
- Canon – Anelva
- Hitachi High-Tech
- Keysight
- KLA Tencor
- Lam Research
- Tokyo Electron
- Ulvac
The main finding is that the increasing demand for nonvolatile memory will drive total manufacturing equipment revenue used for these tools to rise from an estimated $29M in 2017 to between $517M to $792M by 2028. The details behind this forecast are spelled out in the report.
The report also explains techniques that memory makers can employ to reduce the need to purchase more advanced equipment – techniques like self-aligned multiple patterning, which can stretch the capabilities of immersion lithographic scanners from their natural 37nm patterning limit to nearly 10nm.
This post is the fourth of a series on emerging memory technologies, looking at it from several angles, and predicting how these technologies will change both the chip market and the market for the capital equipment used to produce these chips. It consists of excerpts from a recently-released report from Objective Analysis and Coughlin Associates: Emerging Memories Poised to Explode.
There are six sections:
- Why Emerging Memories are Necessary
- Understanding Bit Selectors
- The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.
- Process Equipment Requirements
- Emerging Memory Companies
- Forecasting Emerging Memories
The Memory Guy has provided these to help readers understand the emerging memory technologies and markets. Questions and comments are appreciated.
