Emerging Memories Today: Understanding Bit Selectors

Emerging Memory ParadeThe previous post in this series (excerpted from the Objective Analysis and Coughlin Associates Emerging Memory report) explained why emerging memories are necessary.  Oddly enough, this series will explain bit selectors before defining all of the emerging memory technologies themselves.  The reason why is that the bit selector determines how small a bit cell can get, and that is a very significant component of the overall cost of the technology.  Cost, of course, is extraordinarily important because no system designer would use a component that would make a system more expensive than it absolutely needs to be!

A number of the Memory Guy’s readers may never have heard of a selector. I’ll explain it here.  It’s not complicated.

Every bit cell in a memory chip requires a selector.  This device routes the bit cell’s contents onto a bus that eventually makes its way to the chip’s pins, allowing it to be read or written.  The bit cell’s technology determines the type of selector that is appropriate: SRAMs use two transistors, DRAMs use one transistor, and flash memories combine a transistor with the bit cell so that the transistor both stores the bit and selects it.

Selectors - 2-Terminal 3-TerminalEmerging memory technologies use simpler selectors than are required for today’s leading memory technologies.  They can get by with either two-terminal selectors or three-terminal selectors.  The circuits for both types of cells, with three-terminal and two-terminal selectors, are shown in the graphic to the left.  You can see that there’s not much difference between the two.  In both cases the selector controls the current through the cell either by turning it off with a transistor, or by turning it off when the current reverses with a diode (or something similar).

The rationale behind having a selector is illustrated in the following two diagrams.

The first is a very simplistic overhead view of a resistive RAM (ReRAM) array.  Each bit cell is represented by a dot at the intersection of a Word Line and a Bit Line.  (This drawing has been simplified so that selectors are not shown.)  A Word Line provides the current to select which row of bits is to be read or written.  The Bit Line either reads the bit on that Word Line or it allows a current applied to the Bit Line to program the bit.

A bit can either be in a high-resistance or in a low-resistance state.  I’ll use red for a high-resistance state and green for a low-resistance state because these states either stop the current flow or allow it to pass.

Memory Array

Let’s assume for now that there are no selectors.  If one single bit is put into a low-resistance state and its Word Line (blue) is energized (“Activated”) then the current flows from the Word Line to the Bit Line (green) for the green cell.  No other Bit Lines will receive current because all of their bit cells are in a high-resistance state (red).  Read One Bit in the Array

If any other Word Line is activated no current will flow into any Bit Line because all of the other cells are red, meaning that they are in a high-resistance state.

When other bits are in a low-resistance state, though, trouble crops up.  This is illustrated in the sketch below:Sneak Path

The Output Current that flows down the bit line also can flow up the Bit Line to another cell in a low-resistance state.  This is indicated by a striped arrow.  This low-resistance bit can allow current to flow backwards onto another Word Line, and any bit on that Word Line can direct this errant current onto its own Bit Line indicating that another bit on the activated Word Line is in its low-resistance state when it actually is not.

Imagine that this diagram had a 1,024 x 1,024 array of bits and that these bits were randomly programmed to a 50/50 mix of low-resistance and high-resistance states.  It is hardly likely that any Word Line could be energized without causing every single Bit Line to output a current!

The selector assures that this scenario will not occur.  A diode can be placed in series with the bit cell to prevent reverse currents from flowing onto other Word Lines.  In some emerging memory technologies the diode can be constructed right below the bit cell so that it takes up no space at all.  (In Crossbar’s design the selector is actually a function of the cell’s bit storage mechanism, which is explained in a free Objective Analysis white paper.)

Most memories cannot use a diode as a selector, though, since current must run both ways through the cell.  This will be explained in the next post.  Significant research efforts are still being made to develop good bidirectional selectors that can behave like diodes at low voltages and as resistors at higher voltages.  In most cases, though, it’s far easier to use a transistor, like the one shown above in the three-terminal selector schematic.

Transistor selectors require a lot of space, though, since both Word Lines and Source Lines must run across the array.  This diagram gives a rough idea of how that works:3-Terminal Penalty

Since there is a Source Line for each Word Line, then half as many Word Lines will fit into a given area as with a two-terminal configuration.  This makes the memory cost roughly twice as much as it would with a two-terminal selector.

The developers who work on emerging memory technologies get really excited by technologies that can be selected with nothing more than a diode.  This is a way that these chips can reduce their size and cost, since a chip’s cost is proportional to its area.  Unfortunately, most emerging memory technologies require a forward current to write and a reverse current to erase, so a simple diode won’t work.  Bidirectional selectors are being developed, but another issue gets in the way of them, too.  (I’ll discuss that shortly.)

PCM appeared to have an advantage in this regard.  As will be explained in the next post, PCM programs and erases with a forward current, so a simple diode is all that should be needed as a selector for a PCM cell.  In fact, Intel Fellow Al Fazio, the godfather of 3D XPoint Memory, promoted this viewpoint as recently as two years prior to the announcement of 3D XPoint memory.  It seems, however, that something more is required, as Ron Neale explained in a post he recently published on the Memory Guy HERE.

Selectors are very challenging to get right.  When the 3D XPoint Memory was first introduced in 2015 Micron fellow Scott deBoer said that you can make a ReRAM bit element out of nearly anything, even an eggshell, but the selector is the tricky part.

So what’s so hard about bidirectional selectors?  If a selector has a ratio of “On” to “Off” resistances of 100:1, and there are 100 sneak paths to a Bit Line, then the current from the 100 sneak paths will equal the current from the legitimate path.  In a large array this is almost certain to happen.  The selector must perform significantly better than that.  In most cases, though, a transistor provides both a better “On” to “Off” ratio and it allows bidirectional currents, so it becomes a necessary evil.

All of this has been presented to explain that the selector has a significant influence on the amount of area a memory array consumes, and that the array’s cost is proportional to its area.  For this reason memories that can use a two-terminal selector are much more likely to compete against established memories than are memories that must use a three-terminal selector.

This post is the second of a series on emerging memory technologies, looking at it from several angles, and predicting how these technologies will change both the chip market and the market for the capital equipment used to produce these chips.  It consists of excerpts from a recently-released report from Objective Analysis and Coughlin Associates: Emerging Memories Poised to Explode.

There are six sections:

  1. Why Emerging Memories are Necessary
  2. Understanding Bit Selectors
  3. The Technologies: MRAM, ReRAM, PCM/XPoint, FRAM, etc.
  4. Process Equipment Requirements
  5. Emerging Memory Companies
  6. Forecasting Emerging Memories

The Memory Guy has provided these to help readers understand the emerging memory technologies and markets.  Questions and comments are appreciated.

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