This is the first of a new line-up of Memory Guy posts by Ron Neale. In this 4-part series Ron takes a look at the recently-published analysis by a team from IBM and Yale University (Wiley: Communications of Advanced Materials, Volume 30, Issue 9, March 1, 2018 “Self-Healing of a Confined Phase Change Memory Device with a Metallic Surfactant Layer,” Xie et al) which has cast some new light on the complexity of the movement and element separation in phase change memory (PCM) device structures.
In this series of articles I will briefly review what I think is an important piece of work and its implications for the future of PCM write/erase (w/e) endurance in commercial PCM memory arrays. Today’s production Phase-Change Memory, the basis of the Intel/Micron 3D XPoint Memory, wears out faster than expected. This series will investigate some of the potential reasons for this discrepancy.
Back in 2016 a research team led by IBM claimed the world record for PCM w/e endurance of greater than 2 x 10E12 cycles (ALD-based Confined PCM with a Metallic Liner Toward Unlimited Endurance, Proc IEDM 2016 ). As of today commercially available PCM memory arrays offer w/e endurance of some six orders of magnitude less. The table below comes from another Memory Guy blog post that discusses this.
I have summarized in the figure below the key points of what is possibly the most detailed piece of analytical PCM-related work ever undertaken. The top row of rectangles (yellow) illustrates the route to the record-breaking performance. With the starting point a special confined (~20nm) symmetrical high aspect ratio structure with high density ALD deposited nano-crystalline GST as the active material
Today PCM chip makers perform a special BEOL process step to crystallize the PCM material after it is deposited in an amorphous state. This helps to make the bits’ operation more consistent – without this step the first threshold switching event might be very different from those that follow. In a similar way, this crystallization assures that the first RESET results in amorphous state that is similar to all subsequent RESETs.
For that reason high-density nano-crystalline GST structure is important. Why so? Because it does not allow significant formation of nano-voids during deposition, which are mobile during the memory switching processes and eventually coalesce at the anode causing open circuit device failure.
Other key aspects of the original record-breaking work and of equal importance were the use of a tapered pore structure lined with a high-resistance conducting material.
The IBM experimental procedure and the essential results are briefly described in the lower series of rectangles in the diagram. The detailed TEM analysis and EDX spectral analysis provided the unique view of the composition changes in molten and crystalline GST plus the different associated driving forces.
Two villains were exposed and somewhat surprisingly the movement of antimony (Sb) was perhaps the most serious because its movement creates the conditions which allow voids to form which lead to device failure. Although there is another path to void formation which runs:
Te vacancies → mobile nano-voids → void coalescence → device failure
it would appear the ALD nano-crystallization step minimizes the latter.
However, all was not lost even when failure occurred by the appearance of a void, large enough in diameter to open-circuit the path through the PCM material. The high resistance conducting liner of the pore allowed the passage of a reverse current pulse which healed the device. That result plus the new detail of the changes in composition and element separation leads to the conclusion that bipolar operation might be the route to even longer w/e lifetime or endurance than 2 x 10^12 cycles as indicated in the diagram.
In the next articles in this series I will explore in more detail the different driving forces of element separation in both the PCM and its stacked memory array partner the threshold switch. Then I will move on to the implications of bi-polar operation, threshold switch reliability, and the mammoth task of solving the earlier-mentioned discrepancy between the calculated w/e endurance of commercially-available PCM memory arrays and the demonstrated possibilities.