This is Part 2 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1.
After, in Part 1, summarizing the methodology my next step was to try to bring together in another simple diagram all the detail of the complexity of the movement of the different elements of the phase change memory material at different locations within the memory cell which the IBM/Yale work has disclosed. Movement which leads to the conclusion that bi-polar operation would be means of extending PCM endurance.
In this post’s first diagram (below) the central region provides illustration of the paper’s unique PCM device structure: A high aspect ratio tapered cell lined with a metal conductor. With the two-state memory switching region located (red coloured) roughly at the centre of the taper. This means that, when crystallized, the GST active material acts as pseudo top and bottom electrodes.
The two side panels (a) and (c) illustrate the different forces acting as driving agents in (a) the molten GST during memory RESET and (c) in the crystallized state. In the molten state the two elements which were reported to move in any significant way were tellurium (Te) which becomes a negatively charges anion and moves towards the anode, while antimony (Sb) positively charged becomes a cation moving towards the cathode. Both moved driven by electrostatic forces.
Because of the uniqueness of the structure it was also possible to observe what was happening in crystalline GST during the high-current RESET pulse. High current density electron-wind driven electromigration in metals usually pushes material towards the anode; well for P type materials it appears the situation is reversed and in GST antimony (Sb) and tellurium (Te) are pushed towards the cathode.
All that makes the mathematics easy: A lot more antimony will finish up at the cathode and that proves to be the case. The problem is that the loss of antimony nearer to the anode allows the formation of nano-voids which are mobile and eventually make their way to the anode where they coalesce and the memory device ends its life with an open circuit failure.
The second figure is one view from a comprehensive set of device images in the study which summarises the end point of the formation of a destructive void and the element separation responsible for it.
The IBM/Yale team reported that most of the movement of the elements occurs very quickly within a few switching cycles, creating the pseudo electrodes and the stable operating position for the switching region, in what must be described as a “forming” process. It would seem that the longer term failure-critical problem in the latter stages of w/e lifetime would stem from a more asymptotic movement of the offending elements. This occurs after the earlier rapid movement, and is accompanied by the slower movement of the nano-voids to the end-point of coalescence.
A short burst of reverse pulses was demonstrated to heal or repair an open-circuit PCM device, relying on the metal liner of the “pore” to carry some of the current. This leads to the conclusion that bipolar operation would be the route to the longest possible endurance.
I would imagine it cumbersome to design a PCM memory array to heal cells when they suffer void failure, but if it solves the problem of endurance, then bipolar operation from the very start is the answer.
Because, as reported, the major part of element separation occurs very quickly then it might be expected that any small movement in one direction would be reversed during the following pulse in the opposite direction. The nano-voids would never be able reach the anode and coalesce. When the cell is scaled to lower costs a secondary benefit is that any concerns of element separation by radial diffusion disappear.
While for the purposes of discussion I am allowed to engaged in a healthy dose of speculative design, it might be one step too far to suggest bipolar operation will allow abandonment of the need for ALD high-density nano-crystalline GST, the starting point.
One important further consideration is that PCM SET/RESET pulses are asymmetrical in time and amplitude: The SET pulse is the longer and of a lower current and adorned with a trailing edge, while the RESET pulse is a short high current pulse.
Therefore a move to bipolar PCM operation might require some trade-off to balance the differences in current density and the rates of element separation and movement between the two pulses. Some of the other emerging memory technologies utilize symmetrical write/erase pulse. I will write more on that in a later post.
In the part 3 of this series I will look at how this new complex picture of element separation discussed in parts 1 and 2 might be applicable to the threshold switch, the PCM bit element’s partner in a stacked memory array. Then I will move on to the possible consequences of this research for commercially available devices.
2 thoughts on “Extending the Write/Erase Lifetime of Phase Change Memory: Part 2 – A More Complete View of Element Separation”
Comments are closed.