This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.
Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.
If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.
One little conundrum we must address is: Which version of the threshold switch illustrated in the figure below should be considered? Should it be those where switching involves hotspots and melting, or those which are claimed to be solid state with purely electronic solid-state switching. For the latter it is difficult for me to understand how “S” type negative resistance characteristics can be observed without hotspots or filaments. Anyway let’s first look at the “All Solid State” example. This model assumes that the threshold switch, which is above or below the memory bit in a stacked array, conducts the RESET current, which melts the material in the bit cell, without itself melting.
Now GST is a “p” type material. Let’s assume, for the purposes of discussion, that the arsenic-doped GST is also a “p” type material. (Arsenic doping in this context is used to raise the crystallization temperature.) This would mean that, as a solid hot material, it would be subject to the forces of electro-migration, as is illustrated below in Figures b and c. As explained in Part 2 the antimony (Sb), and to a lesser degree the tellurium (Te), will move towards the cathode and collect there.
At the same time any nano-voids would move steadily to the anode resulting in the end-of-life coalescence.
Hold on! Where do the nano-voids come from? For a threshold switch the material is, and must be, deposited in its amorphous state. As mentioned in Part 1, the void problem was closely aligned to problems originating in the crystal state, with the need for ALD deposition. However there is another route to the formation of nano-voids which start their life as Te vacancies which themselves coalesce into nano-voids and then move on to cause device failure.
It would be expected, in an amorphous material like arsenic-doped GST, that there would be a plentiful supply of Te vacancies, so threshold switches driven by uni-polar pulses could suffer from a”Coalescent Void” type failure in the same way as PCM did in the IBM/Yale study. Any naysayers will have to explain why not
Another consideration is the consequences of the accumulation of Sb and the change in composition at the cathode that might result in the formation of a glass with a lower crystallization temperature or lower threshold switching voltage or both. Either of which could result in a nearest-neighbour memory cell failure.
Those who want to join the “Hot Spot and Melting Threshold Switch Club” then will expect that, during melting, any element separation will be driven by electrostatic forces with Te moving to the anode and Sb towards the cathode. If melting is only localized then a more complicated picture emerges with the mixture of effects described earlier for the PCM.
So is the endurance of the threshold switch the problem for commercially available PCM arrays? Only Intel can answer that question. In Part 4 of this series I will conclude with a look at the good and bad news for the vendors of the present generation of commercially-available PCM arrays and some of the other emerging memory technologies in the light of the discussion presented in this series of articles.