For years SanDisk has been presenting a memory roadmap (this post’s graphic is one rendition) that anticipates a move to ReRAM after 3D NAND has run through its natural life, which was expected to be as little as three generations. This has been backed by the idea that a 3D NAND stack would only be able to reach a certain number of layers before it would encounter difficulties caused by the need to etch a high aspect ratio hole through an increasing number of layers.
The aspect ratio issue is not hard to understand: Let’s assume that the hole in a 24-layer stack has an aspect ratio of 40:1, then a 32-layer hole would have an aspect ratio of about 50:1, and a 64-layer stack would be something close to 100:1. Today’s technology starts to have trouble etching holes with an aspect ratio higher than 60:1.
These high aspect ratios were thought to be the limiting factor that would prevent 3D NAND from continuing for more than three generations. 3D NAND could only have as many layers as the aspect ratio could support.
On a panel that I moderated at this year’s Flash Memory Summit one panelist, Dr. Myoung Kwan Cho of SK hynix, explained that although there is a limit to the number of layers that can be made in a single 3D NAND stack, several stacks can be built one on top of the other on a single wafer. Nobody yet knows how high these stacks can go.
(Update, May 2016: This technique is now known as “String Stacking” and was explained by Applied Materials in Semiconductor Engineering.)
One important point to keep in mind is that I am not talking about multiple chips stacked one above the other – I am rather talking about groups of layers all made on a single chip. Since it’s a single chip, then the costs don’t multiply as they would with a multiple-chip scheme.
All of this means that 3D NAND flash, which many thought had a useful life of three generations, may instead last for decades.
This revelation changes everything.
You may ask if this will make the die too thick. A recent TechInsights teardown reveals that a 32-layer Samsung V-NAND has a stack that is only about 4µm thick. A raw semiconductor wafer is 750-800μm thick, and is commonly back-ground to 50-75µm after processing to allow up to 16 dice to be stacked in a single package. If back-grinding were used on a 3D NAND wafer we would have 675-750µm of extra room for NAND layers before the wafer got back to its original thickness. Using the smaller 675µm number gives us 675µm/4µm = 169 of these 32-layer stacks before the 3D “stack of stacks” became taller than the wafer it began with.
Packages can often accommodate a taller chip than this, so an 800µm thickness is not an upper limit – the limit is probably more than twice that figure for most packages, giving us room for as many as 350 stacks!
Before we reach that point other factors are likely to get in the way. It is already very difficult to perform failure analysis on today’s 32-layer chips, since current tools can’t access the internal layers. Even so, it’s intriguing that 3D NAND may be able to achieve densities that were recently thought impossible.