The following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007. Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end. The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.
Similarities and Differences
These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different approaches to 3D, both of which also differ from Samsung’s currently-shipping V-NAND. Toshiba and SanDisk are staying very true to the BiCS (“Bit Cost Scaling”) charge trap architecture that Toshiba first announced in 2007, while Micron and Intel are using a floating gate design whose details have not yet been revealed. Both Samsung’s V-NAND and Toshiba’s BiCS use a charge trap, which is a convneient way of circumventing any need to pattern a floating gate. Since it is difficult to pattern any vertical structure, most NAND makers see a charge trap as the simplest way to produce a 3D NAND string. Micron and Intel argue that their floating gate alternative takes advantage of years of floating gate experience, a 44-year-old technology. Both the Toshiba 128Gb and the Micron 256Gb 3D NAND chips are 2-bit MLC, while Samsung’s 128Gb part stores three bits per cell.
The Memory Guy feels compelled to make some mention of the timing of these two announcements. Like the Samsung and SK hynix DRAM 8Gb LPDDR4 announcements in December 2013, which were released only an hour apart, the timing of these announcements leads to questions about whether there was a leak from one camp that drove a response from the other. There is no indication of any other triggering event that would have caused these announcements to be synchronized.
Why 3D? Why Now?
Conventional planar NAND flash is approaching its “scaling limit”, a point beyond which it can no longer be cost-reduced by shrinking the production process. 3D NAND is the industry’s approach to continue to cost-reduce NAND flash along its current trajectory for another few generations. For an in-depth explanation of this technology is available on The Memory Guy blog. Objective Analysis publishes reports detailing NAND flash and SSD markets. These reports can be purchased for immediate download from our website.