Hybrid Memory Cube Making Progress

Conceptual Cutaway Drawing of the Hybrid Memory CubeOn Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification.  The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.

As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system.  Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections.  This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption.  The Memory Guy first posted about the HMC in late 2011.

The consortium explains that the HMC interface already has 100 adopters, and that a few OEMs are already evaluating conceptual prototypes.  High-end servers and network switch packet buffering applications are expected to be the first adopters, followed by test and measurement applications.

The new specification adopts two interfaces, each supporting different PC board trace lengths and signalling rates:

  • Short Reach: 8-10″ traces, up to 15Gb/s
  • Ultra-Short Reach: 2-3″ traces, up to 10Gb/s

The Short Reach interface will be upgraded in a later revision, with a goal of reaching 28Gb/s, and the Ultra-Short Reach interface is aiming to get to 15Gb/s.  Separate lines are used for inputs and outputs, improving throughput and allowing devices to be chained for larger memory sizes.

Micron Technology has said that it will sample a Short Reach HMC in the fall, with shipments to begin in 2014.

I see this as a very necessary step forward, that could find adoption in all computing applications by the end of the decade.

3 thoughts on “Hybrid Memory Cube Making Progress”

  1. Hi Jim, can you answer a question about the memory cube and the consortium, if so why is Intel not in the consortium when they worked with Micron on the cube I thought.
    I can’t find anyone who will answer the question.

    1. KJ,

      It took nearly two months of pestering, but Intel finally replied with an official: “No comment.”

      Sorry it’s not a better answer.

      Now that you’ve piqued my curiosity I may dredge around my rumor sources and see if I can come up with some better answer.

      If I do, I will post it here.

  2. Hi Jim, somehow I missed your reply!

    I think if they (Intel) were in the consortium they would have to spill the beans as to what they know and we know they want to maintain their lead. I think the standards are basic as to connections and voltage requirements, maybe even size. Again I am guessing but Intel can bypass all of this by embedding the cube with other stuff, close to their CPU to reap the benefits and that would be good for Micron because the competition would only be for ARM applications yet Micron would still have a crack at them too. We know that Apple will fit in somehow with Micron’s takeover of Elpida which will happen any day now.

    With Micron now announcing they are ready for 16nm planar (Intel’s help with HKMG. connected at the hip) 2014 will be a good year for Micron, I just hope that this won’t put off the cube…

    I thought I read that they would have working examples of the cube this fall for testing and just maybe with Micron’s announcement tomorrow they will address this! I can hope 🙂
    Well those are my thoughts.

    Take care Jim


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