At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of computing equipment, from the lowly PC right through the massive supercomputer. For the time being, IBM has set its sights on using this technology in its Power and OpenPower servers, and in its FlashSystem all-flash storage arrays.
IBM is also pleased with the fact that PCM is a “persistent” memory, that is, it retains its contents even when power is lost. This will bring computing into the world of Storage Class Memory that the company has been heralding for nearly a decade. In IBM’s own words: “Storage-class memory (SCM) combines the benefits of a solid-state memory, such as high performance and robustness, with the archival capabilities and low cost of conventional hard-disk magnetic storage.”
PCM Is Not New
PCM is not a new technology, although it has never found its way into the mainstream. The technology was first explored by Stanford Ovshinsky in the mid-1960s, and was used by the venerable Gordon Moore of Intel to produce a 256-bit research chip that was featured on the cover of Electronics Magazine in 1970.
The trouble with PCM is that it has always fallen between markets. It’s too slow to replace standard DRAM, the memory used for all computers today, and it costs more than DRAM. Researchers have continued to refine the technology, though, because it is universally understood that today’s leading technologies, DRAM and NAND flash, cannot continue to shrink to follow Moore’s Law for much longer. Once either of these technologies reaches its “Scaling Limit” (the point at which shrinking no longer provides a cost advantage) an alternative technology like PCM should be able to fill the void, replacing established technologies.
Last July, Intel and Micron announced breakthroughs that would allow the two companies to produce their new 3D XPoint Memory (which Intel & Micron steadfastly deny is PCM, despite outsiders’ assertions to the contrary) at a cost below that of DRAM. This would change everything.
The 3D XPoint Memory could be used as a new memory layer fitting in the Memory/Storage Hierarchy between NAND flash SSDs and DRAM main memory. To do this, the new technology must be faster than the layer below, but slower than the layer above. It must also be cheaper than the layer above yet more costly than the layer below. PCM has been unable to realize this goal to date because of the fact that its cost is higher than that of DRAM.
While the Intel/Micron approach to cost reduction depends on producing a memory chip with multiple layers of bits stacked one on top of the other (thus the “3D” appellation), IBM has taken a much less costly approach of storing three bits on a single cell, thus tripling overall capacity. This is done by programming the bit cell by varying degrees, something like shades of gray versus a simple black & white “1” or “0”.
According to IBM, the trickiest part of this lies in the fact that the different programming levels drift over time and temperature, which would normally cause these different levels to be confused with one another. (In the graphic at the top, the colored clusters represent individual bits of the IBM part at 25°C – room temperature. The adjacent chart shows their drift with temperature at 70°C.) IBM revealed an approach in its paper to compensate for these issues and allow reliable storage of three bits per cell with high endurance.
The performance data that IBM researchers shared with us proves that the chip can compensate for drift over time and temperature to provide data that is sufficiently reliable for computing applications.
The company is now looking for a partner to license the technology to bring it to market.
A High-Impact Development
The world of computing is moving headlong into a model where a new memory layer will be fit between DRAM main memory and NAND flash SSDs. This is the same phenomenon that occurred when NAND flash prices dropped below those of DRAM: SSDs became a new layer between HDDs and DRAM main memory.
The only challenge will be getting the price of PCM below that of DRAM. Although this has been solved in theory, it will be more difficult in practice. While Micron and Intel believe that they can achieve low enough costs by using the multiple layers of their 3D XPoint technology, IBM has developed a far more economical means of squeezing cost out of PCM with an approach that appears on the surface to be a better solution.
Neither technology will beat out DRAM manufacturing costs until one of them reaches a high enough volume to realize economies of scale. Before then the market must be cultivated by selling PCM below cost.
No matter what, a new memory layer will find its way into all computers relatively soon. As discussed in our report A Close Look at the Micron/Intel 3D XPoint Memory, Objective Analysis anticipates the first market for this technology to develop as a new memory layer in servers, since it will provide better cost/performance than can be achieved by simply adding DRAM.
Although it is a boon that the technology is persistent (that is, it retains data when power is lost) this is a feature that is not supported by today’s application programs, and will probably not be supported for a few more years. It will be another few years after that before such software gains enough popularity to become prominent. We do not see persistence as a key selling point for now, but instead expect for price/performance to be the leading driver for mass adoption.
When we can buy 3D XPoint or PCM chips?
These technologies are for SCM apps as mentioned and might replace DRAM if densities are the same. But to my perception will never replace NAND Flash technologies because of price and density. They can be used as buffer/cache memory inside an SSD, so need for internal capacitors for power down protection (PLP).
Rami, Thanks for the comment.
It’s not clear when Intel and Micron will be able to provide these chips, but their intent is to be in volume by the end of 2017. The chip’s density is supposed to be ten times that of a DRAM processed on the same node.
I certainly don’t expect for 3D XPoint Memory to replace NAND flash, but it should allow systems to use less DRAM. Although these systems will continue to need some DRAM, they can get by with less if they use 3D XPoint. This should reduce the system’s cost while the performance should be higher. Meanwhile, power consumption will be lower.
But we may need to be very patient while Micron and Intel learn how to make this technology cheap enough to fit into the system the way that it should.
A lot of this is detailed in a report on the Objective Analysis website. It’s here: http://objective-analysis.com/Reports.html#XPoint
Jim
Rami,
Thanks for the comment.
Intel & Micron don’t plan to outright replace DRAM with their 3D XPoint Memory, but they do plan to allow systems to operate better with less DRAM. When you add a new tier of memory you get a performance benefit from its size rather than from its speed, so you can use something slower as long as it’s much larger than your DRAM.
Someone once told me that every memory/storage tier should be ten times as large and run at one tenth the speed of the next faster tier. I don’t think it’s actually that simple, but that gives you a rough idea of what these companies want their customers to do.
There’s no reason that 3D XPoint should replace NAND flash – it will cost too much. This is the same reason that NAND flash will not replace capacity HDDs.
As for your first question, I don’t know when you will be able to buy 3D XPoint chips, but Micron has been selling PCM chips since 2008. I have heard that 3D XPoint samples are currently available to key Intel customers.
Best,
Jim
Jim is 100% correct.
there is no line of sight to 3DXP replacing NAND in any measurable amount. It is more expensive well into the future
It allows more random access memory at same price in servers as it is lower cost than DRAM and it’s non-volatile. Example: a 64GB DRAM system becomes 16G DRAM with 128G of 3DXP. The report above shows the impacts on computing and market size … it is significant.
Mark
Jim,
On this comment:
“I have heard that 3D XPoint samples are currently available to key Intel customers.”
Is this the DIMM form factor for 3D XP or another? Besides Diablo and Netlist’s new product announced last week what other SCM solutions are out in DIMM form factor?
Also, you reference the market could be $2B or larger by 2020. Any sense how the market share breakdown may look at that point by product?
Thanks, Jeff
Jeff, Sorry for the late reply.
Intel does say that they have sampled customers with 3D XPoint. This could be one chip each to two customers, or it could be hundreds of chips. My guess is that it’s a very very small number, simply based on how few working chips the company appears to have internally.
Different companies use different definitions for SCM. If you include NVDIMM-N (DRAM DIMMs backed by flash) then Cypress/AgigA, Viking, and Micron join your list, but those products don’t satisfy the price needs that the Diablo, Netlist, and 3D XPoint “Optane” DIMMs are intended to fulfill. These last three products are intended to sell for a lower price/GB than does DRAM.
Jim