Infineon recently introduced a NOR flash chip with an LPDDR interface. Some clients have asked The Memory Guy: “Why would Infineon have done that?”
After all, LPDDR is mostly used in cell phones, and these boot from the enormous NAND flash that’s already in the phone. A byte of NAND is a couple of orders of magnitude cheaper than a byte of NOR, so a cell phone’s not going to use this part.
Infineon tells us that their target market is automotive electronics: engine & transmission control, instrumentation, etc. You don’t need a huge NAND flash if you’re not storing photos, videos, and MP3 files, so a less expensive low-density NOR chip is a good choice in these applications.
The part, which Infineon has named SEMPER X1, supports a system design approach called “Execute in Place” or XIP, that NOR flash proponents have advocated since NAND flash was introduced. With XIP you don’t move the code from the flash to a DRAM or SRAM before executing it, you simply execute the code right out of the flash chip. Of course, with modern processors everything is executed out of the processor’s cache, but still, NOR can provide cache updates directly, while the NAND/DRAM model moves code from the NAND to the DRAM, and then to the cache.
The NOR flash in modern automotive systems is actually a replacement for embedded NOR. New automotive processors are being made on today’s sub-28nm process technologies. These processes all use FinFETs, and nobody’s figured out how to make NOR flash in a FinFET process. This is driving everyone to use either an emerging memory technology as a substitute for NOR, or to use an external NOR flash for code storage.
An emerging memory technology like MRAM, ReRAM, FRAM, or PCM, increases the cost of the processor a good bit, so designers prefer to use an external NOR chip. (This phenomenon is explained in great depth in our Emerging Memory report.)
So far NOR flash has been offered with either of two interfaces: SPI and a parallel SRAM-style interface. Both are slow, especially in comparison to embedded NOR. But today’s increasingly-complex processors are demanding increasing memory bandwidth.
Infineon’s solution is to put an LPDDR interface onto the NOR chip. Not only is LPDDR much faster than existing NOR interfaces, but it can also support the very large off-chip memories that these increasingly-complex processors need. Some MCUs already ship with an LPDDR interface with the expectation that non-DRAM memory chips will soon support LPDDR.
In the company’s product pitch Infineon provides some pretty compelling performance benefits this product provides over DRAM. Some of these are enabled by the company’s use of the charge trap technology that Spansion introduced 20 years ago as MirrorBit. (Spansion was acquired by Cypress, which was in turn acquired by Infineon.)
- A single 32-byte read from the SEMPER X1 is 5 times faster than a similar SPI read, and 20 times faster for random reads, largely because of LPDDR’s faster bus command structure and higher clock rate.
- The part’s read energy consumption is one eighth that of standard SPI NOR flash largely because its read throughput is eight times that of SPI.
- Random reads are 5 times faster than LPDDR4 DRAM random reads, and the data bus is more efficiently used with NOR simply because it does not need to be refreshed as DRAM does.
- When compared to LPDDR DRAM, SEMPER X1 can be trained to the bus timing two orders of magnitude faster than DRAM. (Admittedly, this is something that typically is only a part of the boot-up process.)
Since processors and FPGAs already support LPDDR expect to soon see future announcements for LPDDR NOR flash in The Memory Guy blog. With the introduction of the SEMPER X1 designers now can use both LPDDR DRAM and NOR flash, but SoCs often need other types of memory, so don’t be surprised to see LPDDR SRAM and NAND flash introductions sometime in the future.
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