One memory chip was so important that it was presented three times at this week’s International Solid State Circuits Conference (ISSCC) and that was the Toshiba/SanDisk 128Gb NAND flash. This chip was shown by Eli Harari in Monday’s keynote, then was featured twice in the Wednesday afternoon Nonvolatile Memories session – once by Toshiba and once by SanDisk.
The NAND chip, measuring 170.6mm², is said by both companies to be the densest NAND available. Compared to the Intel/Micron 64Gb 20nm NAND at 118mm², the device gives twice the bits in a 45% larger die area, so the companies’ claim rings true, since the only other NAND makers: Samsung and Hynix, have processes that fall far behind at 27nm and 26nm respectively.
To be perfectly fair, the Intel/Micron device uses a 2 bit per cell MLC, and the SanDisk/Toshiba part uses 3-bit MLC. If we account for that difference then the two parts appear to have similar bit transistor densities per unit area – the Micron/Intel chip has 27 billion usable memory transistors per mm², and the Toshiba/SanDisk chip has 25. Intel and Micron have not yet revealed the die size of their 128Gb 2-bit device, but The Memory Guy guesses that it’s roughly twice the size of the 118mm² 64Gb part. That would be a die size of around 235mm², which is large enough to render it difficult to manufacture. In comparison the Toshiba/SanDisk die size of 170.6mm² should be far more manageable.
This blog post taps heavily into data from the Objective Analysis report: Understanding the NAND Market which can be purchased for immediate download on the Objective Analysis website.
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