The good people at Coventor have graciously allowed me to post their video of the Pipe-Shaped BiCS 3D NAND flash process onto The Memory Guy blog site. Click the image to see it play out.
Coventor tells me that they are the leading supplier of 3D modeling and simulation software for MEMS, virtual fabrication of MEMS, and semiconductors, providing software and expertise to help customers predict the structures and behavior of their designs before they commit to actual fabrication. This video attests to the company’s strengths in that area.
As it stands today, the video is a very simple 2-minute animation with no sound, running through all the steps of the 3D BiCS process without any explanation. At some future point I hope to add annotation and pauses at reasonable times so that it makes more sense to those who don’t have the process memorized. Even without this finessing, it’s a pretty compelling video to watch, and it underscores the sheer complexity of this new process.
Those who haven’t already found and read my series on 3D NAND might want to look at that before trying to comprehend the video. In that series I go into some detail of the process for both Toshiba’s BiCS (in this video) and Samsung’s TCAT or V-NAND 3D NAND processes.
The video was given to me by Sandy Wen and David Fried of Coventor who tell me that it is based on a couple of key technical papers:
- Fukuzumi et al, “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory”, IEDM 2007
- Katsumata et al, “Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices”, VLSIT 2009
Have a click and see what you think. If you’re so moved, post a comment below.
Jim,
Thanks to you and to Coventor for this animation. How many masking steps are involved? It looks like an incredible number.
Bill
Bill, You are quite welcome!
I can’t tell you the number of masking steps, but it will probably become more clear once I get around to annotating the video.
It’s probably far fewer than you think. When the stairsteps are being made only one mask step is used (ideally – in truth there are 3 or more). The photoresist undergoes a “Pull-back” etch for each step without involving any litho steps.
Today NAND makers tell me that the number of mask steps is proprietary. I am sure that will change with time. They do often state, though, that 3D is not as lithography-intensive as its predecessors.
Jim