The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the radiation dose typically applied during a routine sterilization process.
Most memories (and, to a lesser degree, logic) are sensitive to radiation because it can leak a charge off of a floating gate causing the gate’s state to change. This is called a “Soft Error” since this type of bit failure is inconsistent – a “Hard Error” always fails the same way. Radiation causes soft errors in any charge-based memory technology: DRAM, flash (NAND and NOR), SRAM, EEPROM, and EPROM.
To understand this let’s consider a typical flash memory bit cell, shown to the left. A bit is stored by moving electrons onto the floating gate where they are stored. When the cell is accessed by driving a current through the channel then a larger or smaller current will flow through the channel depending on whether or not any electrons have been stored on the control gate. This determines the cell’s state – whether it is a “0” or a “1”.
This post’s first graphic shows what happens when an alpha particle passes through the bit cell: It drags electrons off of the floating gate and into the channel to permanently change the bit’s state. This will happen in any floating gate technology (NAND or NOR flash, EEPROM, and EPROM), in DRAM by eliminating the charge on a bit’s capacitor, or in an SRAM by removing the voltage on one of the transistors in the cell’s flip-flop causing it to become unstable.
Other memory technologies’ bits are insensitive to radiation. These are mask ROM, fusible-link PROM, MRAM (including STT), FRAM, PCM, RRAM (including memristors), and carbon nanotubes. Since there is no stored charge in any of these technologies, an alpha particle is not capable of dragging the charge out of the cell.
The most readily-available of these technologies is MRAM from Everspin, Honeywell, and Aeroflex. Mask ROM is becoming relatively rare and is very expensive unless you purchase hundreds of thousands of chips that all contain the same program. Fusible-link PROM is a very old technology and is only shipped in extremely low densities. I believe that PCM is still supported a little by Micron, but you will probably have trouble getting it from BAE (who specializes in space-qualified versions), STmicroelectronics, Intel, and Samsung. Cypress Semiconductor and Fujitsu sell low-density FRAM. Adesto alone sells an RRAM, which the company calls “CBRAM”.
These companies all understand the advantage that their products hold in high-radiation applications like medical devices. In August Adesto announced that its CBRAM maintains its stored data during the harsh irradiation conditions imposed by the sterilization processes used in medical device manufacturing. These processes exceed dose levels of 50 kGy gamma and E-Beam radiation. Adesto’s management expects to be able to sell its sterilizable CBRAM into applications like wearable electronics, orthopedics, smart syringes & sample containers, and surgical devices that must be sterilized before re-use. The chip will be used to store boot code and reference & calibration data for RFID bio-material tracking, drug delivery and capsule-endoscopy.
Although the development of these new technologies has been funded by investors who anticipate the eventual demise of DRAM or flash memory, the technologies’ near-term markets will be niche applications that can trade off a higher price against some unusual benefit, like radiation tolerance. Because of this, most new technologies are being studied very carefully, but are not widely available. Some day they will replace flash and DRAM.
7 thoughts on “Memory Issues in Space & Medical Applications”
Well, technologies like FRAM, MRAM, CBRAM are not only very expensive, but the strongest hold up against them is their limited memory capacity. The application software will just not fit in just 1Mbit or 4Mbit of memory.
But there are further approaches to guard against the issues of memory-instabilities without having to use low-capacity specialty memory-technologies.
One very simple method is to use an ECC error correction algorithms which works with normal DRAM-memory having memory-capacities in the Gigabit-Range.
ECC is very effectively protecting against low-count soft- and even hard-errors in memory-cells. It is used successfully in all server-systems since the last 30 years.
ECC error-correction is the key-reason why servers (which have ECC) run stable for years, while normal computers or any other electronic devices (without ECC) have transient&randomly occurring erratic functionality or hang-ups.
But ECC alone is not enough when the risk for memory errors is in a higher level, like it is in space where radiation is strong and temperatures also change in extreme levels.
What more can be done?
The intense of ECC correction could be further increased, for example by doing an ECC error correction for every single DRAM chip instead of being able to correct only one bit over the total width of the memory bus (consisting of multiple DRAMs in parallel). This is possible by using the Intelligent Memory ECC DRAMs which have an integrated error-correction performed automatically by the DRAM-IC itself.
Another option to arm against bit-flips is to use DRAMs with larger/stronger memory-cells having ‘more charge per cell’ = a higher signal margin between a logical “0″ or a “1″.
Intelligent Memory’s eXtra Robustness ECC DRAMs (XR ECC DRAMs) are going exactly this way. By twinning two DRAM cells together, the charge per databit as well as the ‘switching barrier’ between a bit being Zero or One get doubled. The result is that these XR ECC DRAM products show a high robustness against external disturbances like radiation, leakage issues and cell-degradation.
And on top these XR ECC DRAMs also have an on-chip integrated ECC error correction algorithm which covers the rare cases where even the twinned cells drop a bit.
Intelligent Memory ECC and also the XR ECC DRAMs are drop-in-replacements to conventional DRAMs. Same pinout, same functionalities, same timings. They can be used on any application that currently use standard DRAMs simply by ‘replacing the DRAM with an ECC DRAM’ and the new functionalities are active.
These new products are sampling in DDR1, DDR2, DDR3 and Mobile DDR technologies now and are not only meant for space or medical devices, but also to protect any other electronic application from random fails and make it ‘reliable as a server’.
Radiation testing of ECC DRAM and XR ECC DRAM is currently under preparation by NASA and other institutions of the space industry. Results are expected early next year.
More information is available at http://www.intelligentmemory.com/ECC-DRAM/
Jim, isn’t this a technology you would like to analyze and report about in more detail?
There’s plenty of detail in your thoughtful comment. Thanks for that!
While the technology you outline is great for DRAM in larger applications, some nonvolatile memory is still necessary to load the program into the DRAM. That’s where most of these technologies fit in.
They are also a better fit for smaller applications, like the medical ones addressed by Adesto. I am talking about applications that don’t use DRAM, and may include five or fewer chips, one of them being an NVM like NOR flash, or something that can store code, and perhaps a little bit of data. In these, a robust ECC scheme would add to the cost and the size of a low chip-count application.
Yes, their low density poses issues in larger applications, since an array of 1,024 1Mb parts will be more costly and will consume a lot more space and power than a single-chip 1Gb memory, and a large array of any component will always have more reliability issues than a single part, but these are tradeoffs that are carefully considered before space applications are fully developed.
I suspect that there are many other system approaches, like the one you explained, that can help get around the use of these new technologies. It must be very different world when you are designing systems for a high-radiation environment!
Thanks for the comment,
What about SONOS memory cell?
Isn’t it more robust to radiations compared to standard double polysilicon Flash memory cell ?
I have heard that SONOS stands up to radiation better than floating gate, and I think that NOR is better than NAND in these environments, but these are all charge-based technologies, and that makes them all susceptible to data loss from radiation.
The other technologies are based on different storage mechanisms that aren’t sensitive to radiation.
Thanks for the comment,
I expect there will be sone difference between NAND, DRAM and SONOS because DRAM and NAND use a free electron while SONOS uses a trapped electron. Based on my experience, SER was caused mainly by leaked charges at the broken PN junction around the store region of DRAM. Maybe, it can kick out a charge from the floating gate at Flash. I expect some improvement due to the trapped charge like SONOS even it’s not perfect. it is necessary to test it. Also, I wonder which mechanism is dominant between breaking junction or kicking out a charge.
Thanks for your feedback. You are right – SONOS, or any charge-trapping technology should hold a charge better than a floating gate technology in radiation.
Still, the new technologies that don’t use a charge are significantly less sensitive to radiation. If you can afford the cost, then they will give higher reliability in a high-radiation environment.
Comments are closed.