Microchip’s Answer to Emerging Memories

Press Photo of two 8-pin mini-DIPs with Microchip logoMicrochip Technology is now shipping a memory chip that has been designed to provide the most popular features of emerging memory chips without using any non-standard semiconductor technologies.  It’s as fast as an SRAM with the nonvolatility of an EEPROM.

Readers may recall that Tom Coughlin and I recently updated our Emerging Memories report.  The chips in that report offer features not commonly found in standard memory types: DRAM, NAND flash, NOR flash, and SRAM.

These new technologies, which include MRAM, ReRAM, FRAM, PCM (also known as PRAM, 3D XPoint, and Optane media), Memristors, NROM, and so forth, all use new materials that must be added to a standard CMOS process, and that drives their cost up.  This is a part of the reason that Intel is losing money on its Optane products.

These emerging memory technologies offer technical advantages over mainstream memories.  All of them are nonvolatile (unlike DRAM and SRAM), and all have write speeds that are close to their read speeds, unlike NAND and NOR flash.  Also, unlike NAND and NOR, they don’t require an erase before a write – ones can be overwritten with zeros and vice versa.

Microchip has taken aim at the emerging memory market with a chip that is made out of standard CMOS but that offers technical features similar to any of these technologies: It’s fast and nonvolatile.  The company has named this technology EERAM.

Internally it resembles an SRAM, so it provides fast reads and writes.  But where SRAM loses its contents when power is removed, Microchip’s EERAM internally transfers its contents to EEPROM bits that are built within the SRAM cells.  A schematic of this appears below (courtesy of Microchip):

Schematic Diagram of an EEPROM cell within an SRAM cell

The SRAM cell at the bottom of the picture is a standard 6-transistor design, and the differential EEPROM cell above consists of two floating gate transistors (the two that look different) that are connected to the SRAM during data transfer by the pair of transistors just below.  The top two transistors power the floating gate transistors when they are active.

Data is transferred to the EEPROM when the chip’s power supply drops below a certain voltage.  This action is powered by an external capacitor devoted to this function.  When power is restored to the chip, data moves back from the EEPROM bits to the SRAM bits, and the capacitor is recharged.

With all of these transistors the cell size is pretty big.  Where DRAM and flash memory cells use only one transistor, and EEPROM uses two, and SRAM 4-6, the EERAM cell uses twelve transistors.  The cost of a chip is related to its area in square millimeters, so the 12-transistor count drives the cost of the EERAM higher.  Microchip says that they plan to sell it for about twice the price of the same-density EEPROM.

This isn’t a new concept.  Simtek introduced a similar chip in the late 1980s.  Simtek’s nvSRAM also provided SRAM functionality to the user and backed up and restored data during power outages with EEPROM bits that were built into the SRAM.   (Simtek was acquired by Cypress Semiconductor in 2008 which was in turn, acquired in 2020 by Infineon.)  The Cypress datasheet appears HERE.

There are differences between the two.  Microchip uses floating gate storage where Simtek’s is a SONOS charge trap.  The Microchip part uses an SPI interface and ships in densities up to 1Mb, while Cypress/Infineon (as of the writing of this post) provides both serial and parallel interfaces and densities as high as 16Mb.

Microchip’s EERAM is sensitive to radiation, as are all floating gate chips, and RAMs to one degree or another.  This is where EERAM differs from emerging memory technologies, all of which are radiation tolerant, which makes them better suited to space applications.  But most applications don’t require radiation tolerance.

At high densities the EERAM’s 12-transistor cell would drive costs so high that it couldn’t compete against any emerging memory technologies, all of which use single-transistor cells.  In fact, some don’t even require transistor, but can get away with a two-terminal selector that not only reduces the area of the cell, but also allows it to be stacked (as in 3 XPoint memory).  Some researchers have even made FRAM and ReRAM cells on a process similar to that used for 3D NAND, the lowest-cost memory in existence today.

All in all, both the Microchip part and Infineon’s version offer reasonable alternatives to the use of many of today’s emerging memory chips.  Over time you can expect for that to change as manufacturers squeeze the costs out of these emerging technologies in embedded applications.  This is all explained in detail in the emerging memory report mentioned at the beginning of this post.

The Memory Guy finds this to be an interesting technology, and will be keeping an eye on it to better understand how it competes against emerging memory technologies in the future.

 

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