Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Hi-k dielectrics: SanDisk disclosed that its new 19×19.5nm NAND is based on a Hi-k material, but the 20nm shipping from Hynix, and Samsung’s leading-edge 22nm process still appear to use silicon dioxide.
So how big is this chip and what does it do to Micron’s production cost per gigabyte? A few quick calculations give us an estimated die size of about 155mm², which agrees with a statement in Micron’s press release that: “The technology could create nearly 6TB of storage on a single wafer.” Assuming a wafer cost of $1,600 (typical of production-volume NAND) that gives us a cost of $0.23/GB, down from the $0.32/GB we estimate for the company’s 20nm product.
Assuming that NAND flash prices remain stable at their current level of $0.50/GB for the next 2 years (Objective Analysis‘ forecast) Micron’s gross profit margin for 16nm wafers would then be about $1,600, an impressive 50%!
It’s pretty easy to see why a flash maker would want to move to a tighter process – the margins promise to be very good.
Objective Analysis follows the NAND flash market very closely, and sells reports on its website detailing the workings of the market with enough detail to allow the reader to predict upcoming trends and price moves.