Micron and Intel hosted an event in San Francisco Tuesday, July 28, to introduce a new memory technology that they have named “3D XPoint”. This technology was explained to be “up to 1,000 times faster, with 1,000 times the endurance of NAND flash” while being significantly cheaper than DRAM.
Some technical details:
- 3D XPoint is a “Fundamentally Different Technology” than current memory types. It’s an ReRAM that uses material property changes for bit storage where both DRAM and NAND use charge to store a bit
- The chip currently stores 128Gb in two stacked planes of 64Gb each, storing a single bit per cell
- Today’s densest production NAND flash chips store 128GB by using MLC, so this chip actually has twice as many bit cells as any production NAND flash
- The companies do not see a clear limit to the number of planes they can stack, but are optimistic about this
- The bulk mechanism can be used to store multiple bits on a single cell (MLC)
- Today’s chip is made using a 20nm process, but can scale well past that
- There is no clear limit of how far the technology can be scaled
- It’s 1,000 times faster than NAND flash and offers 1,000 times NAND’s endurance
- It’s 10 times as dense as today’s “Conventional Memory” (which I suppose to be DRAM)
- This is not intended to replace either NAND or DRAM, but to coexist as a new memory layer between NAND and DRAM
The companies claim that other existing and emerging memory technologies are either nonvolatile and dense, or are fast. They claim that nothing except 3D XPoint provides all three benefits.
[After this post was published, Objective Analysis published a report covering this technology in detail. See The Memory Guy’s blog post, or visit the Objective Analysis website for more information.]
The presenters, Micron CEO Mark Durcan and Intel’s senior vice president Rob Crooke, were very careful to explain that the new technology changed the resistance of the cell material in bulk rather than in filaments as is done in the conductive bridge memories (CBRAM) being developed elsewhere. According to Crooke, filaments have statistical issues that cause problems when they are scaled. This technology uses a “Bulk Material Property Change” to program and erase a bit. All of the atoms in the bit cell change, rather than the few that change in a filament.
The Memory Guy had a lot of questions about this technology, but Intel and Micron aren’t disclosing much at this point. When I asked which of the current alternative technologies this most closely resembled the redirected reply was that there’s nothing at 3D XPoint’s maturity level that’s even close to it. I am not certain how the companies measure maturity, since ferroelectric memories have shipped in hundreds of millions of units since their inception, and Everspin boasts that they have shipped over 50 million MRAM chips. Even if the 3D XPoint memory is PCM based (as many believe, but which the presenters denied) very little PCM actually shipped when both Samsung and Numonyx/Micron were producing that technology.
The diagram for the device at the top of this post is strikingly similar to a 2001 SEM photo presented by Matrix Semiconductor (pictured at left), a firm acquired by SanDisk in 2005, that produced a 3D One-Time Programmable (OTP) memory using a CMOS logic substrate, with the bits stacked above between metal layers.
The audience at the Micron/Intel event was told that 3D XPoint uses a fundamentally new switch that is composed of complicated and different “Breakthrough” materials, as well as a unique chip architecture. Crooke called it: “Something many people thought was impossible and many people gave up trying to accomplish.” Durcan said that the semiconductor processing of this new material is not fundamentally different from existing processes, but it’s really, really tough. To that Crooke added that it’s hard to find this kind of investment and commitment to a project when you aren’t sure that it will really work. The Intel/Micron team believes that they have the commitment and funding to develop a technology that few others could support.
Aside from the technical questions, there is the nagging question of the introduction’s timing. The press release said that 3D XPoint is in production, but if the presenters mentioned production or sampling I missed it, and I was listening pretty carefully for those words. They did commit to independent roll-outs in 2016, which begs a question: What will happen with today’s production parts until that point? I am forced to suspect that very limited numbers of chips are currently being made in R&D runs. New technologies almost always encounter myriad unanticipated issues before they reach economical yield levels. 3D NAND faces this challenge today, and 3D XPoint is likely to be in this position for the next few years.
But why introduce it now? I explored the possibility that a paper had just been accepted for a technical conference, but IEDM and ISSCC are not in that phase today. One acquaintance suggested that it’s a preview of technology that may be more fully disclosed at September’s Intel Developer Forum. My own guess is that these two companies have suffered from Samsung’s successful campaign to create the illusion of technology leadership, and have decided to seize the initiative and beat Samsung to a post-NAND technology.
Yet, they are not positioning it as a post-NAND technology, at least not yet. By saying that it is faster than NAND, but slower than DRAM, and more expensive than NAND but cheaper than DRAM, Micron and Intel are setting the stage to create a new level in the memory-storage hierarchy that fits between NAND flash and DRAM. Any such development will require both platform support (perhaps in the form of a dedicated bus and Memory Management Unit, or MMU, for the new technology) plus software support from applications programs.
It will take some years for all of this to fall into place. Until that time I would expect for this technology to appeal only to niche markets.
10 thoughts on “Micron/Intel 3D XPoint Raises More Questions than Answers”
Would they really put it into production without having sampled this to at least a few large customers and having a few larger orders in their pocket?
Doesn’t this match with the Purley Memory article from May.
I figured you knew something in advance.
So the new memory is only for Xeon level chip that go to datacenter.
even HMC is only for Knights Landing.
More intriguing is that they don’t want this thing licensed or standardized.
probably because they have no clue how to change the architecture of OS and CPU to take advantage.
What happens when PCI 4.0 comes?
In all the HMC presentation, there is not a mention of latency
You’re no doubt referring to my post: What Memory Will Intel’s Purley Platform Use?
I don’t expect for 3D XPoint to reach its price targets in time for Purley. It will take a few years for the companies to make it yield well enough to command a lower price than DRAM. Until then Purley will have to use something more mature. That’s why I expect for Apache Pass to be flash-based.
As for a PCIe card with this memory, I didn’t hear Intel and Micron say anything about PCIe. That mention was buried in one of the audience questions, as I recall.
May be the Purley leak was just to create hype for XPoint but failed.
Ok, I have now seen the webcast on youtube.
– They didn’t really want to commit to any product.
– They kept talking about Memory but really want to replace NAND in the Enterprise.
– High margin low volume application (Enterprise, Military, Supercomputer).
– XPoint was shown at 20 nm wafer while 3D NAND is 40 nm range.
– Whole new class of memory which they have no idea how it will be used, architected, etc.
– CEO vs. General Manager didn’t seem like good optics.
I’m pretty sure I remember them saying they are making it in the factory now, there will be samples to partners before the end of the year, and we will see products hit market in 2016. Based on the info I gathered from their graphics and what I suspect they will have products that use PCIe/M.2 NVMe drives and NVDIMM parts along with embedded solutions with whoever they partner with
NAND already is close PCIe 3.0 4 lanes limit of 3.2 GB/s
the limit goes up to 10 GB/s if you can get 16 lanes.
Intel only provides 40 lanes in the server CPUs.
a single GPU already uses 16 lanes.
PCI 4.0 only doubles the above numbers. Spec is due 2017.
DDR4 is up to 85 GB/s
HMC promises 160 GB/s
again all this 1000x is meaningless in real world
especially when you are going from Gigabytes to Terabytes of data.
Most of the application that promise solution at Terabyte
level are also mere simulation. million x million matrices will
get you what you are look for which is not much.
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