Ron Neale To Share Posts

Ron NealeThe Memory Guy is pleased to begin publishing posts from Ron Neale.  Ron is a specialist in phase-change memory (PCM or PRAM) who has been contributing a lot of analysis of this technology in EE Times.

Ron’s career has centered around phase-change memory.  He was the lead author for the groundbreaking 1970 PCM article in Electronics Magazine, co-authored by Intel’s Gordon Moore (of Moore’s Law fame) introducing the world’s first PCM, a 256-bit device.

Now that the Intel/Micron 3D XPoint Memory has been revealed to use the same technology as Numonyx’ NOR-compatible PCMs, Ron’s analysis of this technology is especially poignant.

Look for posts that feature his keen insight on the technology, its particular challenges, and the ways that PCM is applied to practical problems in advance computing.

Latest White Paper: New Memories for Efficient Computing

A Potpourri of Emerging MemoriesThere has been a lot of discussion in the trade press lately about new memory technologies.  This is with good reason: Existing memory technologies are approaching a limit after which bits can’t be shrunk any smaller, and that limit would put an end to Moore’s Law.

But there are even more compelling reasons for certain applications to convert from today’s leading technologies (like NAND flash, DRAM, NOR flash, SRAM, and EEPROM) to one of these new technologies, and that is the fact that the newer technologies all provide considerable energy savings in computing environments.

Objective Analysis has just published a white paper that can be downloaded for free which addresses a number of these technologies.  The white paper explains why energy is wasted with today’s technologies and how these new memory types can dramatically reduce energy consumption.

It also provides a Continue reading

Storage/Memory Hierarchy 40 Years Ago

1978 Memory/Storage HierarchyLast year I stumbled upon something on the Internet that I thought would be fun to share.  It’s the picture on the left from a 1978 book by Laurence Allman: Memory Design Microcomputers to Mainframes.  The picture’s not too clear, but it is a predecessor to a graphic of the memory/storage hierarchy that The Memory Guy often uses to explain how various elements (HDD, SSD, DRAM) fit together.

On the horizontal axis is Access Time, which the storage community calls latency.  The vertical axis shows cost per bit.  The chart uses a log-log format: both the X and Y axes are in orders of magnitude.  This allows a straight line to be drawn through the points that represent the various technologies, and prevent most of the technologies from being squeezed into the bottom left corner of the chart.

What I find fascinating about this graphic is not only the technologies that it includes but also the way that it’s presented.  First, let’s talk about the technologies.

At the very top we have RAM: “TTL, ECL, and fast MOS static types.”  TTL and ECL, technologies that are seldom Continue reading

Solving 3D NAND’s Staircase Problem

Escher Staircase3D NAND presents an interesting conundrum.  To improve bit costs and continue along the path of Moore’s Law the layer count must increase.  Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever.  The natural way to reduce costs and increase chip density is by adding layers.

But adding layers increases the size of the staircase structure used to access the wordline layers.

With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles.  At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.

An example of a staircase structure can be seen in the Continue reading

Wafer Shortages and DRAM/NAND

Mark Thirsk, Linx ConsultingRecently I have been hearing concerns that an impending wafer shortage might drive today’s DRAM and NAND flash shortages to epic proportions.

The Memory Guy doesn’t pretend to have any understanding of the raw wafer business, so I decided to consult Mark Thirsk, managing partner of Linx Consulting.  Mark has been in this industry for quite a while and has a very good understanding of the ongoing status of the semiconductor materials supply chain.

Mark and I were on a panel together at SEMICON Korea in February, and he presented an interesting chart to compare the costs of different technologies.  I asked him about this chart as well.

Here’s what Mark had to say:

“Our information is that major Continue reading

Amazing 3D NAND Video

Carl Zeiss 3D NAND SEM videoChip reverse-engineering consultant Dick James pointed The Memory Guy to an absolutely amazing 25-second video of a 3D NAND chip.  The video’s made by the Carl Zeiss company.  It’s the second one from the top on this page: https://www.zeiss.com/semiconductor-manufacturing-technology/products-solutions/process-control-solutions/crossbeam-fib-sem.html

The video zooms around a portion of a 3D NAND die as layers are etched away and then restored.  Only the tungsten parts of the chip are shown, with the rest appearing to be empty space.  This serves to clarify it a good bit.  Dick James says that this makes it the equivalent of a 3D x-ray tomograph.

It’s a promotional piece for a Zeiss tool called the “Crossbeam FIB-SEM” that can both image and mill a chip.

Now I doubt that most Memory Guy readers would have a need for this tool, nor be able to afford something which is doubtlessly very expensive, but I am sure that anyone would admire what  it can do.  I certainly find it to be impressive!

Naturally, Dick James was able to identify the chip just by looking at it.  He says that it’s Samsung’s 32-layer part.

Original PCM Article from 1970

For a number of years The Memory Guy has wanted to find a copy of the 1970 article, published in Electronics magazine, in which Intel’s Gordon Moore and two authors from Energy Conversion Devices, Ron Neale and D.L. Nelson, showed that PCM could be used as a memory device.  After all, this is the technology behind Micron & Intel’s 3D XPoint Memory.

The cover of the magazine (this post’s graphic) has been used by Intel to promote its PCM or PRAM chips before those were spun off to Numonyx (now a part of Micron).  Intel, though, didn’t appear to have anything to share but the cover photo.

Electronics magazine went out of business in 1995, and that makes the task of finding archive copies more challenging.

It recently occurred to me that the best person to ask might be the article’s lead author, Ron Neale, who is a regular contributor to EE Times.

I was astounded to discover that Continue reading

Micron and Intel to End NAND Flash JV

Jim Handy in the IMFT fabIt came as a surprise to the Memory Guy on Monday to receive a press release from Micron indicating that Intel and Micron had decided to end their NAND flash partnership.

This agreement, which was begun in 2006, helped the two companies to aggressively ramp into the NAND flash market by combining their resources.  NAND flash makers (as well as DRAM makers) need to make very substantial capital investments to participate in the market, and that’s not easy for a new entrant.  Micron at that time was a very small NAND flash maker, and Intel wasn’t involved in the NAND flash market at all, so neither was in a position to succeed.  By combining their resources the companies were able to become important contributors to the market.

The agreement initially appeared to be modeled after the very successful joint venture that Toshiba and SanDisk enjoyed.  Each company would contribute half of the JV’s capital investment, and the same designs would be used to make both companies’ chips.

Over time Intel found itself in a familiar Continue reading

How 3D NAND Shrinks ECC Requirements

Bit Errors vs. ProcessError Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years.  The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!

Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies?  The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often.  This technique has been used for a long time in both communications channels and in hard disk drives.  Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data.  Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right.  These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today  is a very well-developed science.

Denali Software published a nice Continue reading

Micron’s Super-Fast New 32GB NVDIMM

 

Switch TrackMicron Technology has introduced a 32GB NVDIMM-N.  Perhaps the most important thing about this device is not so much its high density as the fact that it runs at higher bus speeds than competing NVDIMMs, doing 2933 megatransfers per second (MT/s), a speed that Micron representatives tell us is required to support Intel’s Skylake processor.

Up to this point NVDIMM-Ns have been limited to 2400 MT/s, which is fast enough for Broadwell, but which misses the mark for Skylake.  Design is tricky even at this slower speed, requiring a number of expensive high-speed multiplexers in the DRAM’s critical speed path.

“Multiplexers?”  Yes, NVDIMMs use them, even though no other kind of DIMM does.  The Memory Guy can explain why, having just finished a report covering the NVDIMM market and technology.

Here’s a little refresher for those who either don’t remember or never knew that NVDIMM-N requires multiplexers.  The NVDIMM-N looks to the system like a standard Continue reading