DDR DRAM has now been with us for a quarter century, and it has provided a lot of bandwidth. But this standard has become increasingly challenging to scale, and it has already proven to fall short of the demands of the modern AI datacenter.
What’s to become of this fine JEDEC standard in the future? Well if history has anything to tell us, it is far from reaching the end of its life. Every iteration of DDR, from the original DDR through DDR2, DDR3, and DDR4 has been said to have reached the extreme end of the standard’s capability, yet another variant, like today’s DDR5, subsequently comes along to move the industry yet another step forward in the quest to increase DRAM bandwidth.
In order to provide this increasing bandwidth, which is necessitated by processors’ multiplying core counts, the DDR standard has had to make compromises. The most obvious one is the march away from multiple DIMMs per channel for only one or two channels, towards multiple channels with fewer and fewer DIMMs. This was made very clear in a slide that longtime JEDEC member and industry luminary Bill Gervasi made clear in a slide he presented at the FMS show back in 2023, and which appears below.
In this slide, Gervasi shows that the DDR standards have slowly reduced the number of DIMMs that are supported by one DDR channel as the clock rate increased in the following order:
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- DDR: Four DIMMs per channel
- DDR2: Three DIMMs per channel
- DDR3: Two DIMMs per channel
- DDR4: Two DIMMs per channel
- DDR5: One DIMM per channel
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It is currently believed that the yet-to-be-released DDR6 standard will also support a single DIMM per channel, but what is to occur after that? Well, The Memory Guy has heard rumors that DDR7 will continue this progression to support zero DIMMs per channel. This will clearly provide an enormous boost to bus bandwidth as it will drastically reduce the capacitance of the DIMMs, the DIMM sockets, and the bus itself, not to mention the impact on the processor’s pin count and power dissipation! It’s reasonable to expect for data rates to increase from the current tens of gigabits per second to the hundreds virtually overnight.
If this is indeed true, DDR7 will break all bus bandwidth records, potentially removing the “Memory Wall” from the computing lexicon forever.
But there appear to be plans for standards even beyond DDR7 that are being kept under lock and key. Various hints and whispers indicate that DDR8 will follow DDR7 in this progression in a very natural way, with each channel supporting negative one DIMM per channel.
Now, I don’t hope to understand that, much less to be able to explain it to my poor readers, but I will promise to use my extensive network of contacts and Google AI to determine the answer to this perplexing direction, and will certainly do my utmost to provide you an intelligent, logical, and clear answer as to how this is achieved by this date, April 1, of next year.
Lol