Samsung Admits to Needing EUV for Sub-20nm Nodes

Pretty graphic to draw you in to the blog postAbout a year ago a rumor was circulating that Samsung was unable to yield its sub-20nm products without using EUV for the finer processes.  Since The Memory Guy doesn’t traffic in rumors I did not publish anything about this rumor at the time.

On March 25 the company verified the rumor, though, by issuing a statement that: “Samsung is the first to adopt EUV in DRAM production.”  I found it interesting that the company turned something that  was viewed as a weakness into a declaration of leadership.

Does this really put Samsung in the lead, though?  It does not.  The EUV statement tells that Samsung is using this tool for its 1Xnm process technology.  (DRAM makers recently have started to name their processes 1Xnm, 1Ynm, and 1Znm rather than disclose numbers.)  While Samsung has announced that it is sampling 1Znm DRAM, with plans to ramp production in the second half of 2020, Micron Technology is already in production with its 1Znm products.

In fact, in Micron’s most recent quarterly earnings call on March 25 CEO Sanjay Mehrotra stated:

In DRAM, we were the first to introduce 1Z in volume production and expect over half of our bit production to be on 1Y and 1Z by the summer of 2020.

This means that Samsung’s 1Xnm EUV DRAMs are actually two generations behind Micron’s 1Znm chips that don’t require EUV.

Why Isn’t Micron Using EUV?

In May of 2019 Scott DeBoer, Micron’s Executive VP of Technology Development, presented Micron’s technology roadmap and strategy in a webcast that can be viewed here (slides HERE).  On Slides  14 & 15 DeBoer shows why Micron doesn’t plan to use EUV in DRAM until after the last process node that the  company is currently disclosing: 1γnm.  (I have to make a departure here to explain that the 1Xnm, 1Ynm, 1Znm convention ran out of letters, so DRAM makers embarked on another path.  Micron uses Greek letters: 1αnm, 1βnm, and 1γnm, while Samsung simply started over at the beginning of the Roman alphabet with 1anm.  Also note that the last Greek letter “γ”, which unfortunately resembles a “y” in this font, is actually a lower-case Gamma.)

First, DeBoer showed his cost comparison of EUV and optical lithography for each of the currently-disclosed Micron DRAM processes.  In this chart the more advanced processes are on the left, and the older processes are on the right.

This slide is a chart that shows costs for either immersion lithography or EUV for each of Micron's currently-disclosed DRAM processes.

The bottom bullet states: “Prepared for implementation of EUV when beneficial to Micron.”  Micron is indeed expecting to move to EUV, as is implied in the bullet point above this one, but doesn’t see the need to do so until after the 1γnm process.

Micron can avoid the use of EUV through the use of double patterning with 193nm optical lithography.  A careful look at the graphic shows that multiple patterning will be required even with EUV past the 1Znm node, or maybe even for processes past the 1Ynm node.  Although Samsung’s release asserts that: “EUV technology reduces repetitive steps in multi-patterning,” that will only be true for the 1Xnm through 1Znm processes, if even for that long.

DeBoers’ Slide 15 provides a little more detail about why Micron believes that immersion optical lithography is preferable to EUV at processes through 1αnm, and for processes beyond 1αnm.  While EUV provides good uniformity at 1Znm and 1αnm (which implies that yields will be good) Micron believes that its cost competitiveness is inferior.

This is a conceptual chart using red, yellow, and green circles, like a traffic signal, to indicate teh uniformity and cost competitiveness of optical lithography vs. EUV for DRAM processes through 1-alpha nanometers, and for processes beyond 1-alpha.Beyond 1αnm DeBoer tells us that EUV fails on all fronts:  It either has marginal uniformity and inferior cost competitiveness at high doses (high illumination), or it has inferior uniformity and marginal cost competitiveness at low doses.  Either way, Micron finds it to be an undesirable approach for all of the process nodes that Micron currently discloses.

Why EUV Only Makes Sense for  Samsung

Why would Samsung, then, find EUV to be economical?  It’s most likely because Samsung has a leading-edge CMOS logic foundry business and Micron does not.  EUV is required for sub-10nm CMOS logic processes, and Samsung is already producing some 7nm wafers.  Since Samsung already has  EUV equipment in its foundry, the company can use a portion of the EUV tool’s capacity to produce DRAM.  If the DRAM business only uses a fraction of the EUV tool’s capacity, it would only be liable for a fraction of the EUV tool’s cost.

Micron and SK hynix don’t have foundry businesses, so any EUV processing would require these companies to purchase a costly EUV tool solely for DRAM use.  This changes the economics profoundly.  These companies can’t dabble in EUV, using the tool for only one or two layers.  A conversion to EUV becomes a major cost commitment and an EUV tool becomes something to avoid.

So, while it makes sense for Samsung to use a “little bit” of EUV to help its DRAM roadmap to progress, since Samsung’s DRAM business must only pay for that “little bit” of the costly tool, that path is unavailable for Micron and SK hynix.  For these two companies it’s “All or nothing!”

About Those One Million Modules…

In its announcement Samsung boasted that over one million modules have already  been produced using EUV DRAM.  While this sounds like a large number, one million modules can be produced using as few as eight million DRAM chips.  A typical 300mm DRAM wafer produces about 1,000 60mm² chips, so the million modules could be built with the chips from 8,000 wafers.  A DRAM wafer fabrication plant (a “fab”) typically produces 60-70,000 wafers per month (2,000-2,300 wafers per day), so these 8,000 wafers would account for only four days’ worth of production in a typical fab.

While one million modules sounds like a big  number, it’s really not that much when compared to the  size of the  entire DRAM market!

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4 thoughts on “Samsung Admits to Needing EUV for Sub-20nm Nodes”

  1. I would say DRAM canNOT use EUV because the patterns like the bricks are fixed orientation, while EUV cannot help but rotate orientation across the exposure field, +/- 18 degrees.

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