The companies introduced their new “1y” processing node that, according to SanDisk, produces 19nm x 19.5nm cell, versus the earlier “19nm” process (or “1x”) that used a 19nm x 26nm cell.
The graphic for this post (click to enlarge) was presented during SanDisk’s May 5th Analyst Day and compares the 24nm process to the 19 x 26nm process, moving to the 19 x 19nm process, and eventually to “1z” which neither company is yet revealing. After the 1z process SanDisk believes that the company will need to migrate to a 3D NAND structure, which will be the topic of a future blog post. Prior to that the company is certain that the 1z process will provide the cheapest cost per bit of any flash technology, including 3D.
Neither Toshiba nor SanDisk shared the reason why they resorted to an asymmetrical cell for the original 19nm node when IMFT’s 20nm process used a symmetrical cell, a point that Micron and Intel brought up when comparing their technology to those of their competitors. It is my understanding that IMFT’s product required the use of a Hi-k dielectric in place of the more conventional tunnel oxide, and perhaps the SanDisk/Toshiba approach circumvented that requirement.
What is most interesting to The Memory Guy, though, is how the companies use this new technology. SanDisk claims a 25% cell area reduction and Toshiba shares that the new 19nm process will be used later this month to mass produce a 64Gb 2-bit MLC flash that measures a scant 94mm². This gives the chip a Figure of Merit (FOM) of 4.0, which is the tightest layout in the industry for a 2-bit MLC part. Even the two companies’ prior layouts had industry-leading FOMs of 4.1, while competitors’ commercial chips have FOMs ranging all the way to 7.7.
It’s a tight design in a new process that should provide further important cost reductions. Both Toshiba and SanDisk stress that its performance and reliability are good as well, and expressed plans to introduce a 3-bit rendition that Toshiba says will be introduced in the third calendar quarter.
Objective Analysis believes that this new process should do a lot to help reduce NAND manufacturing costs, translating first into better margins for the manufacturers and then to lower costs for end users.