3D NAND presents an interesting conundrum. To improve bit costs and continue along the path of Moore’s Law the layer count must increase. Unfortunately 3D NAND can’t benefit from lithographic scaling; it’s pretty much stuck at 40nm design rules forever. The natural way to reduce costs and increase chip density is by adding layers.
But adding layers increases the size of the staircase structure used to access the wordline layers.
With today’s structures, the addition of layers means adding stairs to the staircase – if you double the number of layers then the amount of die area required by the staircase doubles. At some point the staircase becomes so large that the die has fewer GB/mm² than a die with half as many layers.
An example of a staircase structure can be seen in the SEM photo below. The way this is built was detailed in another Memory Guy blogpost some years ago.
Until now chip developers have worked to devise schemes that lighten this load by cutting steps in 2 dimensions. Macronix has done some wonderful work in this area, and Samsung revealed in August that it is considering the same approach. But while this reduces the problem but doesn’t eliminate it; it’s a partial fix. Until now there has been no compete solution to this problem.
The Memory Guy has recently been told that memory makers’ research teams have found a way to simplify 3D NAND layer count increases.
These researchers decided to borrow an idea that Micron uses to reduce its 3D NAND die size. Micron builds its 3D NAND array over the chip’s peripheral logic (which the company calls CMOS Under Array, or CUA.) Samsung in August revealed that it, too, is performing research in this area, but rather than use Micron’s terminology, the company has named the approach “COP” for “Core Over Periphery.”
But the staircase has, until recently, proven to be a bigger issue. To tackle this, these researchers have decided to use the CUA or COP approach with the staircase. Not only will they stack the memory bits over the peripheral logic, these researchers have worked out a way to put the staircase underneath the memory array. They call this “Staircase on Bottom” or SoB.
The SoB prevents the die area from mushrooming due to an ever-growing staircase. Since there’s plenty of room beneath the array the number of steps available to the SoB is virtually unlimited. This means that the 3D NAND’s layer count is also virtually unlimited, allowing 3D NAND to continue scaling for many, many more generations.
Others think that the approach may not work. One told me that the company has an advantage over its competition: “Only a real SoB can do harm to the other players.”
The approach has certain competitors worried. According to a production manager at one flash maker: “That SoB threatens to come in here and ruin everything we’ve worked for. Our competitors think that they can simply unleash this SoB on us and make us suffer, but we think that they will fail.”
Another NAND maker’s spokesperson told me: “We won’t let just any SoB into our designs. This SoB had better work right the first time or it’s out.”
“The problem this SoB presents us is that it gives us no other options. We’re being forced to work with this SoB!”
The researchers don’t expect for the SoB to be around forever, though. They are investigating other structures that may be more efficient than an SoB. One researcher told me: “We are conducting advanced research on a more sophisticated staircase pattern which will consist of a spiral staircase surrounding the vertical flash strings.” This spiral staircase will be manufactured using self-aligned techniques, allowing it to be constructed using the minimum possible number of lithographic layers, ideally fewer than one.
I am certain to post more about the spiral staircase etch in exactly one year, when April Fool’s Day again rears its ugly head!