Spansion recently introduced a NOR flash that the company boasts is the: “World’s fastest NOR flash memory”. Named HyperFlash, the chip taps into high-speed SPI interface, doubling its width and adding a differential clock to run at an I/O rates as high as 333MB/s.
In this post’s graphic (click to enlarge) Spansion compares the HyperFlash chip’s sustained read rate (right-hand column) to that of (from left to right) asynchronous parallel NOR, single-bit SPI, industry-standard DDR Quad SPI, and Spansion’s faster rendition of DDR Quad SPI, which Spansion tells us, until now, has been the fastest flash on the market. The company points out that HyperFlash is five times the speed of industry-standard DDR Quad SPI while having only 1/3rd the pin count of asynchronous parallel NOR.
The interface is based on a novel device Spansion introduced last December. The company’s “Dual-Quad SPI” consisted of two standard Quad SPI NOR chips in a single package. The two chips’ pins were shared except for the I/O pins (to achieve double the bandwidth) the chip selects, and the clocks. The new HyperFlash uses the same I/O pins, and converts the two separate clocks into a single differential clock input. The second chip select has been discarded, but a read strobe has been added to help the bus master synchronize to the incoming data. By doing this Spansion has maintained pin compatibility across its SPI product line, using the same 8x6mm 5×5-ball BGA for standard SPI, Quad SPI, Dual Quad SPI, and HyperFlash lines.
Who wants such high performance? It ends up that one very important market for this part will be in embedded applications that need Instant-On performance. NAND-based systems have slow boot times, driving engineers to use NOR for the initial boot and NAND for the more sophisticated programs that can be background-booted once screen functionality is achieved. Spansion showed boot times for three different automobile consoles, each with an SPI NOR for fast boot: Standard 50MB/s Quad SPI, Spansion’s faster 80MB/s Quad SPI, and HyperFlash at 333MB/s. Boot times, in the same order, were 4.2 seconds, 2.8 seconds, and 0.7 seconds. Spansion tells me that systems use the HyperFlash to perform XIP (execute in place) by loading lines directly into the processor’s cache without going through DRAM. This is facilitated by the chip’s 96ns initial read access time, or latency. According to the company, systems can be designed with less DRAM when this technique is used.
Nothing exists in a vacuum, and this chip would hardly be useful without controllers that could communicate with it. Spansion tells us that the HyperBus Interface is being implemented by Freescale and other leading system-on-chip (SoC) manufacturers who have yet to be named. The bus is not exclusive to flash. Spansion explains that it is applicable to flash, RAM, and peripheral devices.
It’s intriguing to see NOR speeds boosted by an approach that is somewhat similar to DDR DRAMs. The technology is certainly well established, and Spansion appears to be taking advantage of it to help customers achieve higher performance in embedded systems.