I attended a bit of the SPIE Advanced Lithography conference in San Jose this week. This show is different from my normal fare, since The Memory Guy isn’t all that smart with process technology. Still, there were certain aspects that I wanted to see. Surprisingly, none of the presentations that I attended related directly to lithography: Two were about AI, and two were more about materials processing.
AI and Machine Learning
The two AI plenary presentations were brilliant overviews by two similarly brilliant AI experts: AMD Senior Fellow Allen Rush, and Evangelos Eleftheriou, a Fellow at IBM’s Zurich research center. Although this is another area in which I have no real strength, both presenters made it very clear that AI, and in particular the training process, is a glutton for processor performance and power, with the bulk of the power being used simply to move data from the memory to the processor and back again. Various schemes plan to combine processing with memory to ease some of this burden, but the approaches presented here were very different from the approach I discussed in my recent post about UPMEM. While UPMEM (and others) advocate adding standard CMOS logic to standard DRAM chips, AMD and IBM (and later on, Kioxia) focused on using the linear (analog) properties of resistive RAM to perform matrix algebra for inference (recognition).
Although this didn’t immediately tie to lithography, which is the theme of the show, it was very interesting. What I found later on is that AI is already being used to improve lithography. Papers that were presented at the show had titles like: “Machine Learning and Computational Lithograhy”, “Accuracy Improvement of 3D-Profiling for High Aspect Ratio Features Using Deep Learning”, and “Machine Learning and Hybrid Metrology Using HV-SEM and Optical Methods to Monitor Channel Hole Tilting In-Line for 3D NAND Wafer Production”, and there was even a short course offered called “Machine Learning for Lithography”. A number of other papers didn’t have titles that mentioned AI, but were flagged in the program with an icon that indicated that machine learning was a topic of discussion.
The third plenary talk was by Koji Hashimoto, the General Manager for New Memory R&D at Kioxia Corporation. Kioxia is the new name for Toshiba’s memory spin-out, and Hasimoto gave us something to remember that by with a video about cherished memories. It seems that part of the name “Kioxia” stems from a Japanese word that doesn’t translate well into other languages: “Kioku.” This word expresses memories that have a more human side, powerful, emotional, and nostalgic memories.
That aside, Hashimoto explained that today’s 1TB TLC NAND chips, if they could have been designed using a planar process, would have needed a 7.75nm process geometry. Even though advanced lithography can provide a 7.75nm process it is not possible to make 7.75nm planar NAND because the number of electrons per bit would be immeasurably small. Lithography, then, is no longer a factor in following Moore’s Law, at least not for NAND flash.
Hashimoto explained that this wasn’t simple since a 64-layer 3D NAND flash needs to be manufactured using holes with an aspect ratio of 50:1, which is close to the limit that today’s tools can manufacture. He compared this to the Tokyo SkyTree Tower, the second-tallest tower in the world, which has an aspect ratio of only 10:1. This has driven most producers to use string stacking to allow any number of layers to be used to achieve the desired chip density.
He shared his vision of a future in which the holes in 3D NAND might become 10% closer for each process generation to improve the density increases more than can be done simply through the addition of layers.
One new way to get more bits per chip is to cut the holes in half to double the number of bits per hole. Hashimoto illustrated this with a samurai slashing his sword – a fun visual! He called this approach “Twin BiCS.”
Perhaps the most interesting part of Hashimoto’s presentation was a video created with TEM photography that showed a new way to improve the channel conductivity of 3D NAND flash. (This same video was presented by Yuichiro Mitani at IEDM in December, and I hope that Kioxia will sometime make it available online for all the world to see, because it’s simply amazing!) The video shows how nickle can be used to convert the amorphous silicon in a 3D NAND channel pillar into crystalline silicon. I will be covering that in another blog post soon.
Hashimoto also touched upon the idea that PCM may be useful for AI processors as long as certain issues an be overcome.
The last presentation I attended was from Applied Materials, whose Regina Freed explained “Materials Enabled Patterning”, which, in essence, presented ways to avoid using advanced lithography!
I will cover Ms. Freed’s presentation in more detail in a later post, but in brief, she showed how to achieve tighter process geometries and more precise process control through three approaches:
- Double patterning and quad patterning with more precise control and lower complexity than is possible with current methods
- Lateral etch to achieve tighter tolerances in the width of features, thereby allowing them to be packed more densely
- Selective deposition to more exactly control the location of metal vias. This also allows the vias to become wider, reducing their resistance and increasing their current-carrying ability.
Applied Materials appears to have a very clear vision of future processes that will allow shrinks to continue. It’s fascinating to see how far tool companies can take the industry.
The SPIE conference was interesting and provided a lot of good insight into the path that technologies will follow in the future.