Symetrix: The Next Big Step for FeFETs

Photo of Ron Neale, Renowned Phase-Change Memory ExpertRon Neale enjoyed an extensive e-mail correspondence with Professor Carlos Paz de Araujo of the University of Colorado in Colorado Springs, and founder of Symetrix, about Symetrix’ new approach to ferroelectric memory technology.  In this post Ron provides an overview of that conversation that provides significant insight into why FRAMs hit their limit at 180nm, and why they suddenly have opportunities at the most advanced process lithographies.

Ferroelectric memory was one of the earliest and first of the non-volatile (NV) emerging memory technologies to make significant commercial progress with product design-in wins, followed more recently by PCM and MRAM.

However, in terms of bit density and scaling the technology appears to have plateaued, with bit density for commercial devices hovering somewhere about 8M-bits.  There have been many well-documented options offered, in terms of new materials and device structures, presented in academic research papers, including multilevel cells (MLC) and 3D structures.

The figure below is an illustrative summary of some of those many NV FeFET memory structures and materials that have come and apparently gone over the years.  All, except one, attempted to capitalise upon the attractive possibility of using remnant polarization of ferroelectric materials to directly control the channel of an FET in a monolithic structure.  However, something of a fundamental nature appears to be a limiting factor for commercial FeFET memory devices.

Cross section drawings of various FRAM cell typesAt the time of the recent spin-off of from ARM of Cerfe Labs for the further development and exploitation of Symetrix’ CeRAM, there were some very strong hints that Symetrix also had something significant to offer in relation to the future of FeFET NV memory.

Things have now settled down after the busy period of getting Cerfe underway, so I started an email correspondence exchange with Prof. Carlos Paz de Araujo, University of Colorado, Colorado Springs, the founder of Symetrix and developer of the CeRAM.  I asked if he would provide us with an update, especially in relation to what Symetrix might be able to offer for FeFET memory developers.  Prof. Carlos has in the past been a major contributor to Ferroelectric memory progress.

Initially, in order to provide a background against which we can examine his new work, I asked Prof. Carlos if he would outline for us what he sees as some of the fundamental problems that have limited FeFET progress towards higher bit density and lower lithographic nodes.  He provided the following assessment of those problems:

“FeRAMs have been extraordinarily successful up to the 180 nm nodes.  Billions of devices have been shipped.  In Japan, the entire Train and Subway system has shown that in over 10 years, not a single field failure has occurred.  Also, FeRAMs have FITs of zero, almost infinite endurance, and low power operation.

“What stopped the technology from moving forward was the lack of a Ferroelectric material that could be annealed at temperatures below 400° C.”  (Annealing activates the Ferroelectric Properties.) Prior to HfO2/ZeO2 and the like, there was no Ferroelectric of any kind able to be made to work with annealing below 550° C.  So, with our new Materials, that 40-year barrier has been defeated.

“From the 90 nm node and below, FETs have Nickel Silicon alloys in the source-drain contacts, and the need for this prevented Ferroelectric memories from entering the mainstream.”

[By this the professor is telling us that nickel/silicon alloys were introduced into standard CMOS processes at 90nm and smaller nodes to prevent unacceptable changes in threshold voltage and series resistance with scaling.  In this and in the following paragraph he refers to difficulties presented by the introduction of this alloy, since the high temperatures required to anneal earlier ferroelectric materials (>400° C) caused the alloy to get too close to the source/drain-channel junctions, increasing leakage and changing the threshold voltage.]

“While the use of those alloys helps, for the lower lithographic nodes on down to say 65nm, annealing at temperatures above 400° C results in a degradation of the source and drain doping profiles plus the shifts in FET threshold voltage which are totally unacceptable.

“Recent results, based on the great discovery of manageable ferroelectricity in the HfO2/ZrO2 system with several doping variations, gave hope that the Ferroelectric transistor could be engineered to solve the temperature problem.

“Unfortunately, the metastability and reliability of this approach is a fundamental problem that needs to be addressed.  The typical FET with a ferroelectric gate in deep lithographic nodes is a device with the gate oxide of doped hafnates with thicknesses of around 9 nm and a titanium nitride oxide.  This seems pretty simple and standard.

“But let’s review the situation here. It was never easy to make HfO2 work as a high-K dielectric.  Those involved in that work know that doping the HfO2 is not a very easy thing to do and prevent leakage.  Also the multitude of crystalline phases in this material, once it is doped to achieve enough lattice distortion for polarization is yet another problem for a very thin oxide in direct contact to the Silicon below and metal on top.  It was already well known, from ‘Capacitor only’ tests of this structure, that metastability was a problem.

“The MOS-style capacitor in the gate is also metastable, which makes it extremely hard to have uniform properties across the wafer.  In short, as the field is applied, the film suffers tremendous stress that essentially changes the variety of distorted unit cells (polymorphs) inherent in the effect of the dopant in this material until breakdown occurs.  Those are my views of the fundamental problems.”

I asked Carlos for confirmation of my assumption that he was referring to the stress related to electrostriction effects and not piezoelectric effects?

“Yes , I mean only the electronic electrostriction.”

For the benefit of our readers who may not be familiar with microstriction the figure below is a simplified pictorial explanation.  At the nano-phase level (see inset box) the microstriction stress occurs in both the compression and extension directions as an electric field is applied.  This causes distortion which breaks the crystal structure with a loss (or nullification) of the ferroelectric effect.  The stress effect is proportional to the square of the electric field.  This imposes some limitation on device operating voltages and the use of high levels of remnant polarization. (Although piezoelectric effects are the starting point for ferroelectric memory, they are different from this sort of microstriction and only result in unidirectional stress.)

Cross sections of cells whose heights are compressed or extended, and diagrams of grains subject to electrostrictionProf Carlos replied: “Yes, it is a good illustration”

Note that the diagrams on the right show the ferroelectric crystals as purple pentagons with orderly alignment of the plus and minus signs, indicating polarization.  When these crystals are fractured by electrostriction the order is upset.

The present state of play summarized in the figure below.  The figure illustrates an FeFET cross section.  Present-day device structures replace the earlier perovskite family of first-generation ferroelectric materials such lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT) with various less-than-perfect doped hafnium oxides.

Cross section of an FRAM cell

The figure below illustrates how, by elevated temperature annealing, the useful ferroelectric memory properties for this cell develop.

The hysteresis curve of an FRAM cell follows as a function of anneal temperature (eft to right)The material, as deposited, is not initially ferroelectric, but with annealing, a series of larger and larger P-E sub-loops develop to a maximum.  Annealing at higher temperatures eventually destroys the useful ferroelectric properties.

As mentioned before, there is a trade-off for the underlying CMOS logic between annealing temperature and lithographic node which, to date, has limited commercial ferroelectric memory scaling efforts.  This is shown as the red shaded “lithographic node limiting zone” region in the figure.  The new materials developed by Symetrix move the annealing temperature of the ferroelectric material into the green zone to provide access to the lower lithographic nodes.

Against that background of problems, I raised with Prof. Carlos, the important question: “What will Symetrix now be able to bring to the table as solutions to those and other fundamental FeFET problems?”

“Within the constraints of being in a ‘Patent and Trade Secrets’ window, I can simply say that a material pathway has been found with great consequences to the whole scheme.  This was coupled with a fundamental change in the FET structure.  The combination ‘Material Plus Structure’ has made the device physics very different from what is presently out there in the form of the results presented in certain publications and conferences.  We are working as fast as we can to cover all angles in the patents because, as I know from my over thirty years of involvement in these matters, this is a game changer to all NV and even beyond – especially in the SOC world.”

In another correspondence Prof. Carlos mentioned that his new development is related to changes in materials and structures.  I asked if it is possible that he has developed a material or device structure which allows for electrostriction compensation effects to occur where the electrostriction effects of two phases, or on a larger scale even two parts of the device structure, act against each other to null the damaging effects of the stress?

“Electrostriction can be of positive or negative signs.  The compensation of electrostriction is a bit too complex.  Since the piezoelectric coupling coefficient is larger in most cases, we do not see the effect of electrostrictive strain until we get into the single unit cell and the surrounding crystal distortions caused by the metastable doping scheme that is now being pursued.  Many people believe that they can engineer around that.  I do not believe that it is possible, since every time a pulse is applied to the device, something changes the crystal and domain equilibrium.

I asked what he would suggest is the alternative?

“As I have done in my latest work, I think it is far better to pursue materials with low electrostriction coefficients.  In HfO2 and variants, let us call them the ‘forced’ ferroelectrics, doping with elements like Silicon, Zirconium, and Antimony introduced the strain which makes them attractive ferroelectrics.  However, that same strain, and the component of switching charge required to overcome it, results in the extremely high 2MV/cm switching fields accompanied by some less attractive and damaging consequences.”

I asked Prof. Carlos if he would provide a little more detail of the damaging consequences and the mechanisms.

“The most damaging consequence is the multiphase metastability of those doped HfO materials, followed by the need for high switching fields in thin film devices.  The latter causes things to start to move such as – oxygen vacancies.  Then there is the high deformation of the unit cell with the need to increase applied field in order to get the dipoles to finally align and find a stable saturation point.  This can lead to destructive consequences, which I think you have illustrated in one of your electrostriction figures.”

His reply raises the question as to how this would differ from what we would see in normal thick-film ferroelectrics.

“In normal ferroelectrics and in thick films, the saturation occurs exactly at the coercive field.  But, in thin films, the applied field has to overcome the field under the contact due to the way that the polarization is screened at the metal contact.  This gradient is exactly equal to the negative field from the surface fixed charge within the ferroelectric, in HfO2 doped materials this is a very high field.”

The advantage of a FeFET is that it is a non-destructive readout device, so read cycles don’t contribute to wear.  For this kind of cell surely a write endurance less than read endurance is acceptable.  I asked about this, and he replied:

“Yes, the same limited write endurance occurs and appears to be acceptable with Flash.  But, I believe that what needs to be achieved in a truly revolutionary way is that the ‘write-in’ should be also of high endurance – especially for System-on-Chip and something better than high node Flash.  I think we need to move away from a ‘The more you read, the less you can write’ situation, which makes it difficult to enter into new markets.  Especially those that require low power and non-volatility.  These are the markets that are begging for innovation at the fundamental level.”

I then asked if it might be possible to provide just a little more detail of his new materials that address those problems.

“In our case, we have designed materials that would have coercive and saturation fields that are less than 10% of the large ‘Megavolt scale’ fields that exist in the HfO2 schemes.  One knows not to apply such large fields and not to expect breakdown (and fatigue). Now, as far as the composition of these materials and gate engineering are concerned, that is something that I cannot discuss now.”

However, Prof. Carlos was able to provide us with some C-V plots, shown below, for one of the new materials at 10KHz and 1MHz.  He confirmed that those plots are for a material annealed at 400° C for 1 minute by Rapid Thermal Annealing (RTA) and are the C-V results for a real gate stack of a large area MOS capacitor structure (similar to a MOSFET gate stack) used in their lab work.

Capacitance vs. Volatege curves at 1megahertz and ten kilohertz. They look the same.

The two plots above of capacitance in Farads/mm² at frequencies of 10kHz and 1MHz are for the core region of a FeFET utilising the new low-temperature annealed ferroelectric in a device structure similar to that shown in the FeFET cross section just above. While the C-V plots are similar in shape to polarization versus field (P-E) plots, they are, in fact, derivatives of those characteristics and reflect the charge induced in the FeFET source-to-drain channel by the remnant polarisation of the ferroelectric.

As well as the excellent rectangular form of the C-V loop, for a material annealed at 400° C (a first for a silicon-processing-compatible ferroelectric), other noteworthy features are the low ferroelectric switching voltage of ±1 Volt and the flat saturation part of the C-V characteristics.  The latter provides evidence of the ability of the new material to withstand voltages ten times greater than the switching voltage without any signs of structural degradation.  The 1 Volt switching voltage would be expected to result in a 2 Volt read window for the FeFET.  It is claimed that, with the new materials, it will be possible to engineer the switching characteristics of the new material to values less than 1 Volt.

As a final point on technology, I raised with Prof. Carlos a question on the “Wake up effect”.  In the past this term has been used by proponents of ferroelectric memory devices.  It always appeared to me to be a euphemism for Forming, in order to avoid the negative connotation associated with the use of the F-word.  My question was: “Has the need for FeFET ‘wake up’ limited progress in the past, and have you eliminated the need for any ‘wake up’ it in your latest work?”  His reply:

“‘Wake up’ is the De-pinning of pinned domains in a ferroelectric material.  Pinning can come from many sources – for example, grain boundaries with deep potential wells from oxygen vacancies, or surfaces with similar traps.  In the case of HfO2, the de-pinning may be from the fact that the strain field is such that domains need to be released from an equilibrium position with the strain field.

“To answer your question directly, the materials that we use are designed not to have a need to de-pin and thus there is no wake-up phenomenon.  It has always amazed me to see that there is an almost religious belief in device developers to simply hang on to a single approach to a material and by exaggerated empiricism hope to simply arrive at a device that works.

“I am afraid that this is why we are seeing many papers on the FeFET with simplistic approaches to get the ‘Perfect’ film.  I believe this hinders a real understanding when one ventures outside the standard FET.”

I asked Prof. Carlos if he could perhaps provide us with a little more information with respect to the causes of ferroelectric “Wake up” and the problems he has dealt with in this latest development work, even if he could not disclose the specific details.  He answered:

“Electrostrictive forces, in the types of multi-polymorph films used today, have a deeper well than the coercive energy needed to switch.  It is this that causes the need to apply a larger field in order to de-pin and then switch.  In the classical ferroelectric used in FeRAMs, PZT, the space-charge is created just below the surface.  When the contact is Platinum, the pinning of domains leads to fatigue.  This was removed by using Iridium Oxide electrodes, which placed the screening of the polarization into this semi-insulating metal oxide, instead of into the surface of the ferroelectric.

“This was studied in the ‘80s and lead to the conclusions that led to a practical (yet not perfect) solution.  As it was discovered by Symetrix, and is in use today, the SBT material could use platinum electrodes without any fatigue.  The reason was simply that the screening length internally was much smaller than PZT (0.8 nm versus 50 nm).  This was a major reason for the absence of fatigue in SBT versus PZT with Platinum electrodes.  Screening length (Debye Length), electrode-to-ferroelectric work function difference, and dielectric constant, all contribute to the Ferroelectric capacitor’s reliability.  When combined with metastable and “Polymorphs” that can change and lose their ferroelectricity, the wake-up phenomenon is really just a sign of ‘bad things to come’ as the device is switched.”

We then moved on to the future direction application of the new technology.  Once the company’s patent position has been established, will the plan be for licensing arrangements, as was the case with Prof. Carlos’ earlier ferroelectric memory developments, or will Symetrix develop and market products?  Symetrix is said to have recently made a substantial investment in new capital equipment.  Prof. Carlos explained:

“Symetrix has already exclusively licensed the Arm spin-off company and we are expanding the patent portfolio and making strategic plans on how to license.”

I then asked if his latest invention might allow FeFET-based memory to compete in very high density SCM or persistent class memory (PerCM) applications, to which he responded:

“At this point, it seems very favorable to pursue mainly applications that substitute Flash at a higher node than 32 nm.  It is not a PerCM class because it does pretty much what the capacitor-only FeRAM did, only at a higher density.”

While, for the moment, the need for commercial protection prevents a detailed exposure of Prof. Carlos’ claims, what he has so far disclosed indicates a combination of a new ferroelectric material and device structure changes that will address and solve many of today’s FeFET problems and move FeFET technology forward on a commercial basis.

The possibility of a significant FeFET device structural change is intriguing.  The claims that the new ferroelectric material only requires a low annealing temperature would seem to indicate that maintaining the source/drain diffusion profile is still important.  This suggests to me that it is unlikely that part of the new structure will be significantly different from conventional FeFET memory device structures.

If the claimed structural change is more than just the ability to fabricate smaller devices (although that alone would be a valuable step forward), then those changes are more likely to be in the stack formed by: the gate metal, interface barriers, new ferroelectric material, and FET channel.  The absence of the need for ferroelectric wake-up suggests that interface problems have been dealt with.

Is it possible that the same composition, with a series of sequential processing changes during or after deposition, say ion implantation, can be made to serve multiple purposes in the gate stack?  Time will tell.

I would like to thank Prof. Carlos for the generous use of his time and look forward to the next steps of the full disclosure and the third-party verification of his latest work.

8 thoughts on “Symetrix: The Next Big Step for FeFETs”

  1. Pingback: Blog Review: May 5
  2. Great article. I’m curious based on this comment “Especially those that require low power and non-volatility. These are the markets that are begging for innovation at the fundamental level.”
    Could you provide some examples of these markets or application that would benefit the most?

    1. Dustin, Thanks for the comment.

      The statement that you mentioned was actually from Dr Carlos Paz de Araujo. You will have to ask him about it.

      I will let him know that you asked.


    2. Dustin, thank you for your question. The dominant Nonvolatile Memory is FLASH. It is a complex Memory that is very difficult to scale its fundamental unit storage cell below 32 nm technologies. There are devices that have been scaled to 28 nm but the cell itself is stuck at 32nm. FLASH has low write/erase cycles (100,000 times at a maximum). Typically it has up to about 8 V and around 10 microseconds to write. It can be read faster and with lower voltage and current. It can be stack in many layers, but there is a limit. It is also hard to be integrated into “System-on-Chip” which limits the ability to have more of the smart chips with lower power and integration, as some chips at the core of mobile phones. Also, in Data Silos, it contributes to tremendous heat and problems. So, even though in Solid State Drives it is used and overbuilt many times in size to deal with the wear-out due to limited endurance, everyone yearns for better memory. This is especially true in electric vehicles which beg for memories with better than the 85 C operating temperature. So, you can see that anything that has much more endurance, easier to scale to 14 nm or even below, has 1 V or lower wite voltage and better temperature windows, and can go into SoC’s is attractive everywhere. Thus, this innovation is at the core of many applications and in fact, it is the hope of the new innovation efforts by the US government to revive our industry. For this reason, it is easy to see that as devices as FeFET and CeRAM (our other technology) become available, it is, in fact, a big move aimed at the basic paradigm of what the industry needs to add to the great jumps in ‘Logic” with devices entering 2 nm. The asymmetry between logic (CPUs, GPUs etc) and Memory is a bottleneck for real innovation in the Semiconductor Industry. Thus, to answer your question, it is not that we can say how one or another specific application needs low power. It is a fundamental need for all applications and the industry as a whole to have better nonvolatile memory devices.

      1. Dr. Carlos Paz de Araujo, thanks for the comment. The entire memory hierarchy is built around non-volatility at the lowest level. I think this idea of non-volatility with DRAM like speeds is could be big, I’m curious to see how it will be exploited. I can think of some security concerns but I expect there are some yet to be seen benefits of non-volatility at that level.

  3. Do ferroelectric devices need mechanical stress testing, due to their piezoelectric sensitivity?

    1. Frederick An interesting question. Do you mean stressing the finished chip in some way to test for the effect of any piezoelectric generated voltages on the memory device electrical characteristics or just testing the materials? There is in my article some discussion of the problem of microstriction as one of the fundamental and damaging problems for some ferroelectric memory device materials, I think we included a simple illustration. On the subject of stress I did briefly indicate there is a difference between microstriction and the unidirectional stress from piezoelectric effects.
      The old adage some materials are both ferroelectric and piezoelectric, however not all piezoelectric materials are ferroelectric. If you think for your ferroelectric device structure, piezoelectric effects will be a problem it would seem to be worth testing to find out if your material falls into both camps, for example PZT does. I will try and do a little more digging for you, perhaps Prof Carlos will have more information or further helpful comment.

    2. Thin-film ferroelectric are classified as ceramics. The mixtures of different mono oxides and the like form either a ceramic that is of a crystalline atomic unit cell (like Perovskite ABO3) or a so-called Ceramic which is in technical equilibrium rather than Thermodynamic equilibrium. The most common example as you answered Ron, is PZT. When PZT is Pb Zr(.5) Ti(.5) O3, it is in the ‘Morphotropic Boundary” – this is not in thermal equilibrium, bat rather the “Solid Solution of Lead Zirconate with Lead Titanate, is in technical equilibrium. This is the form of PZT that is most Piezoelectric. For this reason, it is used in the tiny speakers and buzzers in computers and the noises that you hear in a car warning you to put on the seat belts. In the case of memory, PZT is usually on a 45/55 % mixture. It is still technical equilibrium because the stoichiometry is not the same throughout the film. For example, in the grain boundaries, the ratio 45/55 % is not the same. And, switching these internal surfaces can become more or less piezoelectric. From grain boundary to grain boundary, the technical equilibrium may be moved by the applied field into a 50/50% which would be highly piezoelectric.
      I enjoyed in SrBiTaO (SBT) a highly ordered superlattice that was spontaneously created within each grain and modulated the entire z-direction with (Bi2O2)(2+) / SrTa2O7 (2-) which had non-ferroelectric Bi2O2 layers isolating the two perovskite-like Tungsten Bronze (STO) layers. The Bi2O3 was able to compensate lattice defects and homogenized the Ceramic to thermodynamic equilibrium,. So, the material was very low fatigue and charge compensated near the surface eliminated fatigue.

      It is hard to say if Piezoelectricity can be enhanced in such a random environment as PZT boundary conditions. Also, the PZT do form polycrystalline layers that are internally in single Crystal-like polymorphs. But it is still a “Technical Solid Solution” which has piezoelectric, strain and tresses, and Electrostrictive coefficients that are all a function of the applied field. However, a very thin, elastically relaxed film should show a very weak piezoelectric response. So, unless you are dependent on the strain field of multiple polymorphs, you would not test for this.
      In the case, I spoke about (HZO), the technical equilibrium seems to be dominant and things do change with fatigue cycling. So, a serious study of piezoelectric properties and the like may have to be part of a reliability study. Things that are in technical equilibrium relax via thermo-equilibrium.

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