In a November 25 press release Samsung introduced a 128GB DDR4 DIMM. This is eight times the density of the largest broadly-available DIMM and rivals the full capacity of mainstream SSDs.
Naturally, the first question is: “How do they do that?”
To get all the chips into the DIMM format Samsung uses TSV interconnects on the DRAMs. The module’s 36 DRAM packages each contain four 8Gb (1GB) chips, resulting in 144 DRAM chips squeezed into a standard DIMM format. Each package also includes a data buffer chip, making the stack very closely resemble either the High-Bandwidth Memory (HBM) or the Hybrid Memory Cube (HMC).
Since these 36 packages (or worse, 144 DRAM chips) would overload the processor’s address bus, the DIMM uses an RDIMM protocol – the address and control pins are buffered on the DIMM before they reach the DRAM chips, cutting the processor bus loading by an order of magnitude or more. RDIMMs are supported by certain server platforms.
The Memory Guy asked Samsung whether Continue reading “Samsung’s Colossal 128GB DIMM”
One memory chip was so important that it was presented three times at this week’s International Solid State Circuits Conference (ISSCC) and that was the Toshiba/SanDisk 128Gb NAND flash. This chip was shown by Eli Harari in Monday’s keynote, then was featured twice in the Wednesday afternoon Nonvolatile Memories session – once by Toshiba and once by SanDisk.
The NAND chip, measuring 170.6mm², is said by both companies to be the densest NAND available. Compared to the Intel/Micron 64Gb 20nm NAND at 118mm², the device gives twice the bits in a 45% larger die area, so the companies’ claim rings true, since the only other NAND makers: Samsung and Hynix, have processes that fall far behind at 27nm and 26nm respectively.
Continue reading “Inside SanDisk’s & Toshiba’s New 128Gb NAND Chip”