I was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.
The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.
Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out. He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.
For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”
After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion. This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.
Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.
NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”
Micron has announced that it is sampling a new 128Gb NAND flash chip based upon a 16nm process, with production slated for the fourth quarter. To The Memory Guy’s knowledge this is the tightest process available.
The company, with its partner Intel, gained a lead with its 20nm process generation through its use of a Hi-k tunnel dielectric, a new material that replaces more conventional silicon dioxide layer with a new material (Micron won’t say what) that yields the same capacitance with a thinner layer. This has become very important with today’s tight processes because of issues of inter-cell interference.
Other NAND makers are migrating to Continue reading “Micron NAND Reaches 16nm”