Chip reverse-engineering consultant Dick James pointed The Memory Guy to an absolutely amazing 25-second video of a 3D NAND chip. The video’s made by the Carl Zeiss company. It’s the second one from the top on this page: https://www.zeiss.com/semiconductor-manufacturing-technology/products-solutions/process-control-solutions/crossbeam-fib-sem.html
The video zooms around a portion of a 3D NAND die as layers are etched away and then restored. Only the tungsten parts of the chip are shown, with the rest appearing to be empty space. This serves to clarify it a good bit. Dick James says that this makes it the equivalent of a 3D x-ray tomograph.
It’s a promotional piece for a Zeiss tool called the “Crossbeam FIB-SEM” that can both image and mill a chip.
Now I doubt that most Memory Guy readers would have a need for this tool, nor be able to afford something which is doubtlessly very expensive, but I am sure that anyone would admire what it can do. I certainly find it to be impressive!
Naturally, Dick James was able to identify the chip just by looking at it. He says that it’s Samsung’s 32-layer part.
Error Correction Codes, ECC, are not only important to today’s NAND flash market, but they have been a cause of concern to NAND users for a number of years. The Memory Guy has been intending for some time to write a low-level primer on ECC, and I am finally getting it done!
Why is ECC necessary on NAND flash, yet it’s not used for other memory technologies? The simple answer is that NAND’s purpose is to be the absolute cheapest memory on the market, and one way to achieve the lowest-possible cost is to relax the standards for data integrity — to allow bit errors every so often. This technique has been used for a long time in both communications channels and in hard disk drives. Data communication systems can transfer more data using less bandwidth and a weaker signal over longer distances if they use error correction to restore distorted data. Hard disk drives can pack more bits onto a platter if the bits don’t all have to work right. These markets (and probably certain others) have invested a lot of money in ECC research and development, and as a result ECC today is a very well-developed science.
Denali Software published a nice Continue reading “How 3D NAND Shrinks ECC Requirements”
Yesterday The Memory Guy learned of an amazing article in DigiTimes about a 3-6 week shutdown at Toshiba’s Yokkaichi NAND flash fab line. According to the story Toshiba’s production was shut down for 3-6 weeks accounting for a production loss of 100,000 wafers. Another article in PC Games N converted that to lost bytes and came up with the number 400,000 terabytes.
Some quick math shows the errors in both of these articles.
First of all, the wafer stoppage. The Toshiba/SanDisk Yokkaichi Joint Venture wafer fabrication complex processes a little over 2 million wafers per year. Divide that by 52 weeks and you find that’s about 40,000 wafers per week, so 100,000 wafers would be 2.5 weeks’ output, not 3-6 weeks.
The number of bytes that PC Games N published takes a little more math. According to TechInsights Toshiba’s 15nm 128Gb MLC chip has an area of 99mm². That gets you a little over 10TB/wafer. The company’s 48-layer TLC 256Gb part should produce about twice that. Yet, if you divide PC Games’ Continue reading “Did Toshiba REALLY Lose 3-6 Weeks’ Production?”
Yesterday’s news really underscored the race currently underway between 3D NAND makers to produce higher layer counts than one another.
Intel produced an announcement in which VP Rob Crooke bragged that: “Intel has delivered the world’s first commercially available 64-layer, TLC, 3D NAND solid state drive (SSD). While others have been talking about it, we have delivered.”
The announcement explained that the new Intel SSD 545s could be purchased at Newegg beginning that day.
The Memory Guy received Intel’s announcement at 10:02 AM Pacific Time. By 3:11 PM, five hours later, there was another announcement in my “In” box, this time from Western Digital (WDC).
WDC’s e-mail announced the development of the the SanDisk/Toshiba next-generation BiCS4 3D NAND technology, with 96 layers. The companies expect to begin to sample a 256Gb part to OEM customers in the second half of 2017 with production starting by the end of next year.
One has to wonder if WDC was Continue reading “3D NAND: “I Have More Layers than You Do!””
In a letter to shareholders released today, Toshiba finally clarified its plans for restructuring the company. Since January 18 there have been numerous rumors that Toshiba planned to spin its memory business off or sell it outright. Today’s letter indicates that this hasn’t been decided yet. In fact, other than to call a late March shareholder vote and to reveal a restructuring, the letter discloses extraordinarily little.
In a nutshell Toshiba has decided to isolate the memory business (including the SSD business but not the HDD and image sensor businesses) into a separate wholly-owned subsidiary. There was no mention of either the recently-shrinking Discrete business or the System LSI business, which has been in a steady decline for the past decade. Click on this post’s graphic to see how each of the company’s semiconductor businesses has been doing.
The intent appears to be to groom the subsidiary to be spun off or sold, but this has not been expressly stated. Instead Toshiba simply states that: “The Company is still considering various structures with a view to an injection of third-party capital.”
The letter reiterates Toshiba’s prior position that the memory business Continue reading “Toshiba Decides to Split Off Memory Business”
On Saturday, June 18, Samsung’s Xian fab, the only facility in the world currently producing 3D NAND flash, suffered a power failure. How much of a problem is this?
The answer really depends upon who you ask. An article in the Financial Express quoted Samsung as saying that it would have a minimal impact, and that full-scale operations should resume in a few days. The article also said that Samsung estimated that the wafer loss would be below 10,000 wafers.
Assuming that the entire loss consisted of Samsung’s most advanced 48-layer 256Gb 3D NAND a 10,000-wafer loss would be less than 1% of total industry gigabyte shipments.
Korea Times quoted an anonymous fund manager who said: “The one-time incident will cost Samsung up to 20 billion won, which is very minimal. It won’t make heavy impact on Samsung’s chip business and the entire industry.”
According to Korean news source Chosenilbo the outage was caused by Continue reading “Samsung Power Glitch – Is It Important?”
Samsung has finally introduced the 3-bit 3D NAND chip it revealed at last August’s Flash Memory Summit. This announcement was made in the form of an SSD announcement.
For those who were unable to attend the Flash Memory Summit, Samsung’s Senior VP of Memory R&D, Bob Brennan, announced in his keynote speech that a 3D 32-layer V-NAND, a chip that would achieve twice the chip density of planar NAND, was entering production and that SSDs would follow in a month. Now, two months later, Samsung has announced those SSDs.
This week’s release reiterates Continue reading “Finally! Samsung’s 3-Bit V-NAND Arrives”
The good people at Coventor have graciously allowed me to post their video of the Pipe-Shaped BiCS 3D NAND flash process onto The Memory Guy blog site. Click the image to see it play out.
Coventor tells me that they are the leading Continue reading “Making 3D NAND Flash – Animated Video”
Samsung has announced that the company’s newest memory fabrication plant (Fab) in Xi’an, China has “begun full-scale production operations”, adding that: “The new facility will manufacture Samsung’s advanced NAND flash memory chips: 3D V-NAND.”
I immediately asked whether the plant will build products other than 3D NAND, and the company has replied that this will be the only product produced in the Xi’an plant. What Samsung has not said is what is meant by “full-scale production operations.” Typically wafer fabs start with a very low production capacity as new tools are being qualified, only ramping to high-volume production a year or more after initial production.
Samsung points out that production has begun a mere 20 months after initial groundbreaking, which is quite Continue reading “Samsung Begins Operations at its Xi’an Fab”
I was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.
The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.
Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out. He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.
For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”
After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion. This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.
Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.