Arsenic – The Memory Guy Blog

University of Lancaster Invents Yet Another Memory

The Memory Guy recently encountered some stories in the press about “UltraRAM” which is the name for a new type of NVRAM developed by researchers at Lancaster University in the UK. These researchers published one paper last June in Nature: Room-temperature Operation of Low-voltage, Non-volatile, Compound-semiconductor Memory Cells, and another just this month in the IEEE’s Transactions on Electron Devices: Simulations of Ultralow-Power Nonvolatile Cells for Random-Access Memory.

According to the papers, the new Continue reading “University of Lancaster Invents Yet Another Memory”

Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch

This is Part 3 of a short Memory Guy series in which contributor Ron Neale continues to explore the possible future impact on PCM memory performance, especially write/erase endurance, building on the results of the IBM/Yale University analysis outlined in Part 1 and Part 2.

Part 3 of this series of articles triggered by the recently published PCM device analysis by a team from IBM/Yale University, moves to a look at its possible implications for the arsenic doped GST threshold switch. Although the threshold switch was not part of the IBM/Yale work, the implementation of the call for bipolar operation of PCMs means there will be a requirement for a threshold switch whose durability matches that of the memory with which it will be associated in a memory array.

If the study’s finding for PCM can be applied to the arsenic-doped GST threshold switch which is used in today’s commercially-available PCM arrays then the threshold switch might just be the weak link that accounts for the poor endurance of commercial PCM memory arrays.

One little conundrum we must address is: Which Continue reading “Extending the Write/Erase Lifetime of Phase Change Memory: Part 3 – Failure Modes for the Threshold Switch”

New Materials Solve Key 3D NAND Issue

At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material. This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.

For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.

imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.” Further they report that on-state current (I_ON) and transconductance (g_m) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation. The device’s characteristics are shown in this post’s graphic.

The consortium reports that the current through the Continue reading “New Materials Solve Key 3D NAND Issue”