(The following is an update of a post that originally ran on 29 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
Some of my readers have asked: “How is 3D NAND Continue reading “How Do You Erase and Program 3D NAND?”
(The following is an update of a post that originally ran on 8 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
One of the thornier problems Continue reading “3D NAND: How do You Access the Control Gates?”
(The following is an update of a post that originally ran on 8 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative Continue reading “An Alternative Kind of Vertical 3D NAND String”
(The following is an update of a post that originally ran on 1 November 2013. It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore Continue reading “3D NAND: Making a Vertical String”
Back in 2013, when Samsung announced its V-NAND, the first production 3D NAND, The Memory Guy blog carried a series of posts to explain the new technology and the reason it was so necessary.
Now that the inventors of this technology have been honored with the FMS Lifetime Achievement Award, I decided that it was time to refresh that series of blog posts. Once a week for the next nine weeks I will be reissuing a post in this series. I hope that these will Continue reading “What is 3D NAND? Why do we need it? How do they make it?”
At the IEEE’s IEDM conference last week Belgian research consortium imec showed an improved “gate first” 3D NAND that replaced the conventional polysilicon channel with InGaAs, Indium Gallium Arsenide, a III-V material. This new technique opens the door to higher layer counts in 3D NAND, allowing denser parts to be made in support of further cost reductions.
For those unfamiliar with the term, the “gate first” approach is the foundation of Toshiba’s BiCS NAND, and presumably Micron’s floating gate 3D NAND.
imec explains that “Replacing poly-Si as a channel material is necessary, as it is not suitable for long-term scaling.” Further they report that on-state current (ION) and transconductance (gm) of the III-V channel was better than that of polysilicon devices, without any programming, erase, or endurance degradation. The device’s characteristics are shown in this post’s graphic.
The consortium reports that the current through the Continue reading “New Materials Solve Key 3D NAND Issue”
NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”
