How Do You Erase and Program 3D NAND?

How FN Tunneling Works. Cross section of a floating gate transistor. A word balloon on the control gate says "Strong Positive Potential", and word balloons on the source and drain say "Strong Negative Potential." Arrows show how the current would travel from the source and drain through the tunnel oxide to leave electrons on the floating gate, indicated by little circles, as the current tried to reach the control gate.

(The following is an update of a post that originally ran on 29 November 2013.  It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)


Some of my readers have asked: “How is 3D NAND Continue reading “How Do You Erase and Program 3D NAND?”

An Alternative Kind of Vertical 3D NAND String

Samsung's TCAT 3D NAND flash(The following is an update of a post that originally ran on 8 November 2013.  It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)


My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate.  This post will look at an alternative Continue reading “An Alternative Kind of Vertical 3D NAND String”

3D NAND: Making a Vertical String

Toshiba's Original BiCS Diagram - IEDM 2007(The following is an update of a post that originally ran on 1 November 2013.  It was republished in 2024 as a part of a series to honor the 3D NAND inventors who have received the 2024 FMS Lifetime Achievement Award.)


Let’s look at how one form of 3D NAND is manufactured.  For this post we will explore Continue reading “3D NAND: Making a Vertical String”

Samsung’s View on Charge Trap Flash

Samsung's Cheese analogy for Charge Trap FlashAt the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology.  I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.

One key attribute of most 3D NAND approaches is the use of a charge trapping layer.  This has to do with the difficulty of manufacturing sideways floating gates.

Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”

Hynix and Spansion Join Forces

Spansion and SK Hynix AllianceSK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.

These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact,  Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”

The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.

The companies have also agreed to cross-license their patent portfolios.

You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”

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