Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?”
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”
My prior 3D NAND post explained how Toshiba’s BiCS cell works, using a silicon nitride charge trap to substitute for a floating gate. This post will look at an alternative technology used by Samsung and Hynix which is illustrated in the first graphic, a diagram Samsung presented at a technical conference. This cell also uses a charge trap.
Let The Memory Guy warn you, if the process in my prior post seemed tricky, this one promises to put that one to shame!
Part of this stems from the use of a different kind of NAND bit cell. You can shrink flash cells smaller if you use a high-k gate dielectric (one with a high dielectric constant “k”) since it Continue reading “An Alternative Kind of Vertical 3D NAND String”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”
SK Hynix and Spansion have announced a strategic NAND alliance under which Hynix will serve as a foundry for low-density SLC NAND chips made for Spansion using Hynix’ advanced processing nodes.
These products, aimed at the embedded market, should serve to strengthen Spansion in a market in which the company thrives. In fact, Spansion expressed this very well in their press release, citing: “Spansion’s recognized customer support and commitment for longevity of supply, which is highly valued in the embedded market, where Spansion has established relationships.”
The new chips will be manufactured in “4x, 3x, and 2xnm” process technologies.
The companies have also agreed to cross-license their patent portfolios.
You may be asking yourself: “What does Hynix Continue reading “Hynix and Spansion Join Forces”