Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.
This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.
For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism. My friend and processor guru Nathan Brookwood tells me Continue reading “Intel to Use Micron Hybrid Memory Cube”
Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
During SK hynix’ October 29 earnings call the company further clarified the status of its Wuxi fab line that was hit by a fire on September 4. In brief, the company may miss its expected end-November date to recover to full operation.
Interestingly, although DRAM bit shipments declined by 2% because of the fire, revenues increased by 3% thanks to price increases caused by the resulting tight DRAM supply. This gave the company a revenue boost taking total semiconductor revenues from ₩3.93 trillion ($3.54B US) in the second quarter to ₩4.08 trillion ($3.66B US) in the third quarter. Not only was this revenue a record number for SK hynix, but margins also reached a record high.
All in all, it was a very good quarter, despite the fire, and perhaps because of it.
The company disclosed that restoration of the air ventilation system and the clean room have been Continue reading “Hynix Recovery – Not so Soon?”
Today Micron Technology announced that it is sampling the Hybrid Memory Cube (HMC) a DRAM packaging technology that it has been working on with the HMC Consortium.
Micron has been pushing to rapidly advance the HMC’s development and seems to have reached this point in an impressively brief time, given the complexity of the technology. It has only been two years since the first public appearance of the HMC at the 2011 Intel Developer Forum.
Some pretty advanced technology was used to make this product. DRAM processes are not very good at Continue reading “Micron Samples Hybrid Memory Cube”
On Tuesday the HMC Consortium (that’s short for “Hybrid Memory Cube”) announced that members have agreed upon a specification. The consortium has been moving rapidly, meeting its targets despite the revolutionary nature of the interface.
As a reminder, this technology stacks multiple DRAMs in a single package with a logic chip at the base of the stack that performs all the signalling to the rest of the system. Signals between the DRAMs and logic chip use through-silicon vias (TSVs) as interconnections. This allows the technology to deliver 15 times the performance of DDR3 at only 30% of the power consumption. The Memory Guy first posted about the HMC in late 2011.
The consortium explains that the HMC interface already has 100 adopters, and that a few Continue reading “Hybrid Memory Cube Making Progress”
DRAM manufacturers often refer to “The Windows Bump” – a phenomenon that is believed to occur after every release of a new version of the Windows operating system. According to this theory DRAM demand increases for a period following an introduction.
An example: in a recent article Kingston VP Scott Chen said that an increase in sales for Windows 8 might help raise DRAM demand, leading to more stable prices.
Demand is expected to pick up on the upcoming launch of Windows 8 tablets and Ultrabook PCs later in the second half of 2012.
Does the Windows Bump really exist? The Memory Guy thought Continue reading “Does the ‘Windows Bump’ Really Exist?”
NAND prices have increased since July, and that appears to have helped Samsung to increase its memory revenues in the past quarter. That comes as a welcome change!
As this post’s graphic illustrates the company has has seen downward-trending memory revenues for five of the past six quarters, but Q2 revenues increased by ten percent. Interestingly enough, the last quarter-to-quarter increase was a miniscule 0.3% one in Q2 of 2011. It looks as if growth tends to regularly occur in Samsung’s second quarter.
Last quarter’s revenue growth helps to debunk rumors that Samsung was Continue reading “Samsung Revenues Reflect NAND Price Increase”
Someone recently asked The Memory Guy to comment on a projection that NAND flash bit consumption was headed into a period of reduced growth. This appears to have stemmed from a comment made by another memory analyst.
This drove me to compile this report’s graphic, which compares historical bit growth for DRAM (bottom, black line) against that of NAND flash (upper red line). Although NAND started out with astronomical annual bit growth of nearly 250%, it declined in 2011 to around 70%. This brings it closer to DRAM’s rate that ranges around 50%.
This is not cause for alarm – when the NAND market was very small bit growth was expected to be high. Large demand upturns could be relatively easily accommodated. Today’s multibillion-dollar capacity additions require more careful planning. This is the Law of Large Numbers.
We are at a point where NAND bit growth will probably settle into a range similar to that of DRAM. Consumption will be limited by economics, since production increases involve huge capital expenditures.
So, in a way, we are more headed out of a period of declining bit growth than going into one.
Objective Analysis has produced a report: Understanding the NAND Market, that is available for immediate download from our website.
A colleague recently asked me to verify that the DRAM business has had zero net profits over its entire history. This is something he had heard at a technology event that really surprised him.
I have often heard this story myself, for DRAM as well as for flash (both NAND and NOR) but I had never put in the time to test the assertion.
This statement is certainly attention grabbing, and because of that presenters everywhere will find some way to include this “fact” into their slideshows. “But is it true?” he asked me.
Well, I can’t call myself “The Memory Guy” without having an answer to this question, so I Continue reading “Is DRAM Really a Profitless Business?”
Today Samsung announced that its chips are used exclusively to make up the 324-terabytes of DRAM in Germany’s new Leibniz Supercomputing Centre SuperMUC supercomputer.
Samsung’s release tells us that the SuperMUC, the most powerful supercomputer system in Europe, is an IBM System x iDataPlex dx360 M4 server built using over 18,000 Intel Xeon CPUs and over 80,000 4GB DRAM modules from Samsung. (Simple math makes this out to be 82,944 modules.)
That looks like a lot of silicon! Let’s see how much that might be.
A 4GB parity DRAM module would use nine 4Gb DRAM chips, which Samsung appears to Continue reading “Samsung DRAMs in Massive Leibniz SuperMUC”