At a technical conference hosted by the IEEE this week IBM announced the results of nearly a decade of research in which its scientists have been investigating the emerging technology known as “Phase Change Memory” (PCM). The scientists presented a means of successfully storing three bits per cell for the first time, while also addressing all of PCM’s challenging idiosyncrasies, including resistance drift and temperature drift.
Commonly referred to by the erroneous nickname “TLC” for Triple Level Cell, this technology squeezes three bits of data into the space of a single bit, essentially cutting the cost per gigabyte to about one third of that of a standard memory chip making it closer in cost to flash.
With this step IBM expects to help drive a new memory layer into existence, one that will fit between the cheap and slow NAND flash used in SSDs and the fast but expensive DRAM used for main memory. Such a layer would improve the cost/performance of all types of Continue reading “IBM Jumps on the “New Memory” Bandwagon”
Objective Analysis has just introduced a new report that you might want to consider: A Close Look At The Micron/Intel 3D XPoint Memory.
The report covers the Intel-Micron 3D XPoint memory and includes Intel’s new Optane support products that are based on this technology. The report explains the technology and its special manufacturing challenges. It includes details of how 3D XPoint memory will be used, and provides an analysis of the benefits of its persistent nature.
Forecasts project how the market will develop and include optimistic and pessimistic forecast scenarios. Particular attention has been paid to its impact upon the DRAM, SSD, and other markets. Finally, the report analyzes different end-market segments to predict how this technology will impact each of them.
The Memory Guy, report author Jim Handy, will present the report’s findings during the Pre-Conference Primer of the Storage Network Industry Association (SNIA) Storage Developer Conference (SDC) this Sunday, September 20, at 2:00 PM, In Santa Clara, CA.
This breakthrough report is based on Continue reading “New Report: 3D XPoint Memory”
There has been quite a lot of interest over the past few days about the apparently-inadvertent disclosure by Intel of its server platform roadmap. Detailed coverage in The Platform showed a couple of slides with key memory information for the upcoming Purley server platform which will support the Xeon “Skylake” processor family. (A review of this post on 7/13/17 revealed that The Platform’s website has disappeared. The above link and the next one no longer work.)
One slide, titled: “Purley: Biggest Platform Advancement Since Nehalem” includes this post’s graphic, which tells of a memory with: “Up to 4x the capacity & lower cost than DRAM, and 500x faster than NAND.”
The Memory Guy puzzled a bit about what this might be. The only memory chip technology today with a cost structure lower than that of DRAM is NAND flash, and there is unlikely to be any technology within the leaked roadmap’s 2015-2017 time span that will change that. MRAM, ReRAM, PCM, FRAM, and other technologies can’t beat DRAM’s cost, and will probably take close to a decade to get to that point.
Since that’s the case, then what is this mystery memory? If we think of Continue reading “What Memory Will Intel’s Purley Platform Use?”
The following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007. Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end. The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.
Similarities and Differences
These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different Continue reading “Four New Players Join 3D NAND Market”
The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”
Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.
This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.
For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism. My friend and processor guru Nathan Brookwood tells me Continue reading “Intel to Use Micron Hybrid Memory Cube”
NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”
This series has looked at 3D NAND technology in a good deal of technical depth. The last question to be answered centers around the players and the timing of the technology. A lot has been said about the technology and its necessity. Will everyone be making 3D NAND? When will this big transition occur?
This post will provide an update as of its publication (13 December 2013) to show each company’s current status, to the best of The Memory Guy’s understanding. Readers may want to refer back to the earlier posts in this series, as well as to a June 2013 Nikkei TechON article that gives a good review of the 3D NAND alternatives that have been presented at various technical conferences.
Let’s start with Samsung, the largest producer of NAND flash today. Just prior to Memcon 2013 last Continue reading “3D NAND: Who Will Make It and When?”
Some of my readers have asked: “How is 3D NAND programmed and erased? Is it any different from planar NAND?”
In a word: No.
(Before I get too far into this allow me to admit that The Memory Guy doesn’t understand quantum physics, so I will be presenting this only to the depth that I understand it. There will be no band-gap diagrams or equations to wrestle with.)
Both 3D NAND and planar NAND use Fowler Nordheim Tunneling (FN) to both program and erase. This differs from NOR flash which programs bits using Continue reading “How Do You Erase and Program 3D NAND?”
One of the thornier problems in making 3D NAND is the job of connecting the peripheral logic (the row decoders) to all of those control gates that are on layers buried somewhere within the bit array. Remember that the control gates are the conductive sheets of polysilicon or tantalum nitride at various depths in the chip.
The problem boils down to this: You can’t run connections from each layer up or down the side of the chip to get to the CMOS circuits below. Instead you have to create a terrace structure to expose and connect to each layer.
These connections are made by etching a stair-step pattern into the layers and sinking Continue reading “3D NAND: How do You Access the Control Gates?”