The following is an excerpt of an Objective Analysis Alert sent to our clients 7/13/15.
A July 13 Wall Street Journal article disclosed that China’s state-owned Tsinghua Unigroup has bid to buy Micron Technology for $21 a share or $23 billion, which would make this the largest-ever Chinese takeover of a U.S. company.
Objective Analysis has been telling our clients for the past few years that either China or India would create a new DRAM/NAND manufacturing company, especially since memory chip makers have enjoyed a long period of profits, and this usually motivates outsiders to invest in new DRAM makers. We did not anticipate an acquisition.
Countries with heavy industry typically move into the semiconductor business during an extended upturn, and become DRAM suppliers since DRAM is an undifferentiated commodity. Commodities sell almost solely on price and success is based on little more than manufacturing strength. This is a business model that industrial economies understand.
In addition to Micron’s tangible assets, including Continue reading “Is Micron Being Acquired?”
For the past ten months DRAM prices have been undergoing a steady slide. Is the market in a crisis? Not really!
Today’s low spot price of $4.30/GB puts us on a par with February 2013, a full two years ago (see chart). DRAM makers have done a lot to reduce their production costs since that time, so their margins this quarter will be much better than they were in the first quarter of 2013.
But we are still a very long way from the bottom of the last market downturn. In late 2012 spot prices reached a low of $2.52/GB, a full 41% lower than today’s lowest spot prices.
The Memory Guy models the production costs of leading memory chips, and DRAM manufacturing costs have been decreasing for the past several years at an average annual rate of about 30%. That means that costs today are about half of what they were two years ago, and one third of their level this time in 2012.
So even though today’s Continue reading “DRAM Prices Down, But Not So Bad”
The following is excerpted from an Objective Analysis Alert sent to our clients on March 26: On March 25 SanDisk and Toshiba announced sampling of their 3D NAND flash technology, a 128Gb (gigabit) 48-layer second-generation product based on the BiCS technology that the companies pioneered in 2007. Pilot production will begin in the second half of 2015 with meaningful production targeted for 2016. This release was issued at the same time that Intel and Micron were briefing the press and analysts for their March 26 announcement of their own 3D NAND offering (pictured), which is currently sampling with select customers, and is to enter full production by year-end. The Micron-Intel chip is a 32-layer 256Gb device, which the companies proudly point out is the densest flash chip in the industry.
Similarities and Differences
These two joint ventures (Intel-Micron and SanDisk-Toshiba) are taking very different Continue reading “Four New Players Join 3D NAND Market”
Last week Micron and IBM announced that Micron would be IBM’s main supplier of NAND flash chips. The week before Micron announced a strategic agreement with Seagate to supply NAND flash. Why all this activity?
It comes down to today’s budding NAND flash shortage and the fact that suppliers tend to groom their customer lists when supplies get short.
Neither IBM nor Seagate represent the enormous opportunities that major consumer electronics firms like Apple do. Since many NAND suppliers are very cost-focused they look for customers that need very little support and purchase in high volumes.
IBM and Seagate look for a lot of support, and, since they both ship mostly enterprise flash systems or SSDs, they consume relatively small unit volumes of NAND flash chips.
These companies need to have an understanding of Continue reading “NAND Sourcing Changes as Supplies Tighten”
Inotera recently announced earnings and posted an impressive 55% gross margin. Inotera is a pure-play DRAM maker, so it’s not too difficult to estimate the company’s process geometries based on its financials.
The Memory Guy thought it might be interesting to determine what I could from the 55% gross margin number.
First of all we can estimate Inotera’s manufacturing cost/GB based on the gross margin and an assumption about the company’s sales price/GB. The WSTS price per gigabyte for November was $7.83. Assuming that Inotera’s ASP was equal to this number, then at a gross margin of 55% the company’s cost/GB would have been $3.52.
Inotera’s acts as a foundry for Micron Technoogy. If Inotera sold to Micron at some lower price, then Inotera’s production costs would necessarily be proportionally lower to maintain the same gross margin.
Using the WSTS price: At a processed wafer cost of $1,600 (my rule of thumb) a $3.52/GB cost would require 454 8Gb dice to be produced Continue reading “Backing Out DRAM Process Rules”
The Memory Guy was recently asked about using memories in a satellite. What would be a good technology to use in a space application?
The problem with space is that there is a lot of radiation. Radiation on the earth’s surface is lower because it is stopped by the atmosphere, but in space there is an abundance of radiation that interferes with most semiconductors. Radiation is also a concern in certain medical applications where a memory must maintain its contents while undergoing sterilization through irradiation. Experiments on conventional flash memories have shown data loss at only 2% of the Continue reading “Memory Issues in Space & Medical Applications”
Intel and Micron today announced that the new version of Intel’s Xeon Phi, a highly parallel coprocessor for research applications, will be built using a custom version of Micron’s Hybrid Memory Cube, or HMC.
This is only the second announced application for this new memory product – the first was a Fujitsu supercomputer back in November.
For those who, like me, were unfamiliar with the Xeon Phi, it’s a module that uses high core-count processors for problems that can be solved with high degrees of parallelism. My friend and processor guru Nathan Brookwood tells me Continue reading “Intel to Use Micron Hybrid Memory Cube”
I was recently directed to a very interesting blog post written by 3D technologist Andrew Walker of Schiltron in which he compares two NAND flash chips that were presented at the IEEE International Solid State Circuits Conference (ISSCC) on February 12.
The post, titled Samsung’s V-NAND Flash at the 2014 ISSCC: Ye Distant Spires… is on the 3D InCites website.
Dr. Walker puts a lot more time and effort into his graphic representations of 3D NAND chips than do others (The Memory Guy included) and this makes it much easier to understand the issues he points out. He shows us that Samsung’s 3D NAND cell is about 5 times the size of a 40nm planar NAND cell and about 30 times that of Micron’s 16nm planar cell, and that the 3D NAND’s physical area is unlikely to change with any future 3D technology generations.
For this and other reasons (given in the article) he states that the Samsung V-NAND is “an impressive achievement but not a realistic foundation for the future.”
After having compiled my series on 3D NAND I can appreciate Dr. Walker’s opinion. This is certainly going to be a difficult technology to master, and it could be quite some time before the cost structure for 3D NAND can compete against that of today’s planar technologies.
Give the Walker post a quick read and judge for yourself whether we are at the brink of a 3D conversion or if this technology can be expected to slip out a few years.
NAND flash is the process leader in memory technology, and this puts it in a very challenging position: It must ramp to high volume production using techniques that have never been tried before.
The graphic for this post (click to enlarge), supplied by ASML, the semiconductor industry’s leading lithography tool supplier, illustrates the challenge of migrating from one process node to the next. Across the bottom, on the X-axis, are representative process nodes ranging from “2D-45”, or two-dimensional (planar) 45nm NAND, to “3D-5x”, or three-dimensional 5xnm NAND. Below these numbers are the year of volume production.
The vertical axis, labeled “Tolerance” represents the minimum Continue reading “Why NAND is So Difficult to Scale”
Every so often something very strange happens that puzzles The Memory Guy. On December 29 (or Dec. 30 in Seoul) something odd occurred.
I received two e-mails, one from SK hynix at 3:55 PM Pacific Time, and one from Samsung exactly one hour later. Both were press releases.
The SK hynix release was titled: “SK Hynix Developed the World’s First Next Generation Mobile Memory LPDDR4”. It announced that the company is sampling its 20nm-class 8Gb LPDDR4 DRAM to customers.
The Samsung release was Continue reading “Did SK hynix Beat Samsung to the 8Gb LPDDR4?”