Let’s look at how one form of 3D NAND is manufactured. For this post we will explore the original design suggested by Toshiba at the IEEE’s International Electron Device Meeting (IEDM) in 2007. It’s shown in the first graphic of this post. (Click on any of the graphics for a better view.)
Toshiba calls this technology “BiCS” for “Bit Cost Scaling.” The technique doesn’t scale the process the way the world of semiconductors has always done to date – it scales the cost without shrinking the length and width of the memory cell. It accomplishes this by going vertically, as is shown in this post’s first graphic.
This takes a special effort. This is where the real Continue reading “3D NAND: Making a Vertical String”
At the Flash Memory Summit yesterday ES Jung, PhD, EVP & GM for the Samsung R&D Center, explained the inner workings of Samsung’s new V-NAND vertical NAND flash technology. I will shortly be writing a series to explain what a 3D NAND is since there is little on the web that gives clear details about the technology.
One key attribute of most 3D NAND approaches is the use of a charge trapping layer. This has to do with the difficulty of manufacturing sideways floating gates.
Dr Jung delighted the show’s audience by explaining that a standard floating gate is like Continue reading “Samsung’s View on Charge Trap Flash”
Just in case anyone thought that NOR flash was not going to get any denser, Spansion announced a single-chip 8Gb parallel NOR today. This product, built using Spansion’s MirrorBit technology on a 45nm line is not only the densest monolithic NOR chip on the market, it’s also the NOR flash with the finest process technology.
Spansion’s GL-T product is aimed at applications that need high densities at read speeds faster than those that NAND flash can deliver. Spansion tells The Memory Guy that read performance is 95MB/s and program performance is 1.8 MB/s.
Sampling will commence in December, with production in the first quarter of 2013.